Marvin Onabajo

Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications

An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (G_m-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. An OTA design with the proposed broadband linearization method has third-order inter-modulation (IM3) distortion better than -74 dB up to 350 MHz with 0.2V¿¿ input, 70 dB signal-to-noise ratio (SNR) in 1 MHz bandwidth, and 5.2 mW power consumption. The distortion-cancellation technique enables an IM3 improvement of up to 22 dB compared to a commensurate OTA without linearization. A proof-of-concept low-pass filter with the linearized OTAs has a measured IM3 < - 70 dB and 54.5 dB dynamic range over its 195 MHz bandwidth. The standalone OTAs and the filter were fabricated on a 0.13 ¿m CMOS test chip with 1.2 V supply.

External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range

This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed. The PSR performance is improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. The effectiveness of the PSR enhancement technique is experimentally verified with an LDO that was fabricated in a 0.18 μm CMOS technology with a power supply of 1.8 V. The active core chip area is 0.14 mm2, and the entire proposed LDO consumes 80 μA of quiescent current during operation mode and 55 μA of quiescent current in standby mode. It has a drop-out voltage of 200 mV when delivering 50 mA to the load. The measured PSR is better than -56 dB up to 4 MHz when delivering a current of 50 mA. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively.

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback

This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs. Fabricated in a standard 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW from a 1.8 V supply, and occupies a die area of 2.6 mm2. The modulator has a measured SFDR of 78 dB and in-band IM3 under -72 dB with -2 dBFS two-tone signal power.

A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers

In this paper, a practical current injection based built-in test (BIT) technique for impedance-matched RF low-noise amplifiers (LNAs) is proposed. A current generation circuit injects the RF test current at the gate of the LNA; this approach has the advantage that the matching network is not affected by the test circuitry. The technique can be used without design changes to measure the voltage gain during on-wafer test and to measure S21 during final test in the presence of gate inductance and package parasitics. Furthermore, the current injection testing technique enables accurate gain measurements in order to detect faulty impedance matching networks. The proposed current-based BIT requires an on-chip voltage source, two on-chip power detectors (PDs), and an accurate external resistor. On-chip or external equipment resources are only required to measure the dc output of the PDs. As a proof of concept, a 2.1-GHz inductor-degenerated common-source LNA with a gain of 23.9 dB was designed in 0.13-mum CMOS technology together with the BIT circuitry (14% area overhead). The gain predicted by the current injection RF BIT agrees with the simulated gain using corner models within 0.8-dB error.

Electrothermal Design Procedure to Observe RF Circuit Power and Linearity Characteristics With a Homodyne Differential Temperature Sensor

The focus in this paper is on the extraction of RF circuit performance characteristics from the dc output of an on-chip temperature sensor. Any RF input signal can be applied to excite the circuit under examination because only dissipated power levels are measured, which makes this approach attractive for online thermal monitoring and built-in test scenarios. A fully differential sensor topology is introduced that has been specifically designed for the proposed method by constructing it with a wide dynamic range, programmable sensitivity to dc, and RF power dissipation, as well as compatibility with CMOS technology. This paper also presents an outline of a procedure to model the local electrothermal coupling between heat sources and the sensor, which is used to define the temperature sensors specifications as well as to predict the thermal signature of the circuit under test. A prototype chip with an RF amplifier and temperature sensor was fabricated in a conventional 0.18-μm CMOS technology. The proposed concepts were validated by correlating RF measurements at 1 GHz with the measured dc voltage output of the on-chip sensor and the simulation results, demonstrating that the RF power dissipation can be monitored and the 1-dB compression point can be estimated with less than 1-dB error. The sensor circuitry occupies a die area of 0.012 mm2, which can be shared when several on-chip locations are observed by placement of multiple temperature-sensing parasitic bipolar devices.

Strategies for built-in characterization testing and performance monitoring of analog RF circuits with temperature measurements

This paper presents two approaches to characterize RF circuits with built-in differential temperature measurements, namely the homodyne and heterodyne methods. Both non-invasive methods are analyzed theoretically and discussed with regard to the respective trade-offs associated with practical off-chip methodologies as well as on-chip measurement scenarios. Strategies are defined to extract the center frequency and 1 dB compression point of a narrow-band LNA operating around 1 GHz. The proposed techniques are experimentally demonstrated using a compact and efficient on-chip temperature sensor for built-in test purposes that has a power consumption of 15 μW and a layout area of 0.005 mm 2 in a 0.25 μm CMOS technology. Validating results from off-chip interferometer-based temperature measurements and conventional electrical characterization results are compared with the on-chip measurements, showing the capability of the techniques to estimate the center frequency and 1 dB compression point of the LNA with errors of approximately 6% and 0.5 dB, respectively.

Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip

This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements. Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters;Includes built-in testing techniques, linked to current industrial trends;Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches;Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.

Significantly Enhanced Inductance and Quality Factor of GHz Integrated Magnetic Solenoid Inductors With FeGaB/

We report new high quality factor (Q) integrated GHz magnetic inductors based on solenoid structures with FeGaB/Al2O3 multilayer films, which show significantly enhanced inductance and quality factor at GHz frequencies over their air core counterparts. These inductors show an excellent high-frequency performance with a wide operation frequency range 0.5-2.5 GHz, in which the inductance is flat and the peak quality factor can reach ~20. The inductance of the magnetic inductor shows >100% enhancement compared with that of the same size air core inductor. These novel GHz inductors with high inductance and Q enhancement show great promise for applications in radio frequency integrated circuits.

{\rm Al}_{2}{\rm O}_{3}

This brief addresses the realization of an on-chip block for built-in testing of RF transceivers with the loopback method. Design issues and measurement results are discussed, giving practical insights into closing the signal path between transmitter (Tx) and receiver (Rx) sections. The circuit is intended for cost-efficient production testing of RF front-end blocks with on-chip power detectors and bit-error-rate analysis at baseband frequencies for integrated transceivers operating in the 1.9- to 2.4-GHz range. It can provide 40-200 MHz Tx-Rx frequency shifting and 26-42 dB continuous attenuation while consuming a 0.052-mm2 die area in 0.13-mum CMOS technology and ~ 12 mW of power when activated in test mode.

Multilayer Films

This paper presents a subthreshold cascode low-noise amplifier (LNA) with inductive source degeneration and third-order linearity enhancement. The LNA architecture includes an inductor and a capacitor at the gate of the cascode transistor for partial cancellation of third-order distortion components. This design method enables third-order intermodulation intercept point (IIP3) and 1dB compression point (P1dB) improvements of 4.8-11.2 dB and 7.1-11.6 dB respectively (depending on the process corner case) compared to a commensurate LNA without the linearization method. A 2.4 GHz LNA was designed and simulated using 0.13 μm CMOS technology. In the typical corner case, the linearized LNA achieves -2.0 dBm IIP3, -13.5 dBm P1dB, 18.2 dB power gain, and 4.54 dB noise figure with a power consumption of 0.24 mW.