Mary J. Saccamango

A dynamic body discharge technique for SOI circuit applications

It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.

An SOI floating body charge monitor technique

SOI pass transistor circuits are vulnerable to initial-cycle parasitic bipolar current which can cause speed degradation or functional failures (Kuang et al, 1997; Lu et al, 1997). This paper describes a novel floating body charge monitoring method which effectively reduces the sensitivity of transient response in the initial cycles and improves circuit robustness and noise margin without using body-contacted devices. In doing so, we avoid the area penalty, issues of contact resistance, and modeling difficulties associated with body contacts. The charge monitor mimics the circuit configuration and biasing characteristics of a particular circuit, such as the MUX topology, which is prone to bipolar current-induced initial-cycle slowdown. When excess body charge is detected by the monitor circuit, an additional discharge path is automatically enabled to provide more switching current and thus minimize timing variation.

A floating-body charge monitoring technique for partially depleted SOI technology

This paper presents a floating-body charge monitoring technique, which does not require the use of body contacts on the device being monitored. A charge monitor is placed along side with the circuit that is susceptible to the floating-body effects in partially depleted (PD) SOI CMOS circuits. It mimics the circuit topology and operating history of a concerned circuit, specifically the worst-case body voltage of the critical device(s) under consideration. The monitoring is achieved by intentionally triggering a parasitic bipolar current pulse and setting the a state recording latch, which subsequently activates the speed recovering circuitry that compensates the loss of performance at critical circuit nets due to the presence of parasitic bipolar current. Implementation examples are given and described. This technique restores performance and improves timing robustness of the MUX-type and SRAM bit line circuits by minimizing the delay degradation or variation from parasitic bipolar currents.

Effect of emitter contact materials on high-performance vertical p-n-p transistors

Ion-implant doped polysilicon, in situ doped polysilicon, and in situ doped ultrahigh vacuum chemical vapor deposition (UHV/CVD) low-temperature epitaxial silicon emitter contacts were used to fabricate shallow junction vertical p-n-p transistors. The effect of these materials on emitter junction depth and on device characteristics is reported. A DC current gain as high as 45 was measured on polysilicon emitter devices. Regardless of emitter contact material, all devices showed sufficiently high breakdown voltages for circuit applications. However, only for ion-implant doped polysilicon emitter devices was the narrow-emitter effect observed through the emitter-collector punchthrough voltage, emitter resistance, and current gain measurements.<<ETX>>

Laser‐driven boron diffusion into a Si epitaxial layer from a p+ boron‐doped Si substrate

Experiments are described in which ∼0.2‐s‐wide argon laser pulses are incident on a 6‐μm‐thick n− Si epitaxial layer. Local melting and refreezing of both the layer and a small volume of the underlying p+ boron‐doped Si substrate occur. In the molten phase, boron diffusion from the substrate is sufficient to make a low resistance path between the front surface and the substrate, with a nearly uniform dopant concentration of 5×1018/cm3. The melted/recrystallized front surface diameter is ∼50 μm. Unique features and applications of this type of substrate contacting are discussed.