Somnuk Ratanaphanyarat

Effect of emitter contact materials on high-performance vertical p-n-p transistors

Ion-implant doped polysilicon, in situ doped polysilicon, and in situ doped ultrahigh vacuum chemical vapor deposition (UHV/CVD) low-temperature epitaxial silicon emitter contacts were used to fabricate shallow junction vertical p-n-p transistors. The effect of these materials on emitter junction depth and on device characteristics is reported. A DC current gain as high as 45 was measured on polysilicon emitter devices. Regardless of emitter contact material, all devices showed sufficiently high breakdown voltages for circuit applications. However, only for ion-implant doped polysilicon emitter devices was the narrow-emitter effect observed through the emitter-collector punchthrough voltage, emitter resistance, and current gain measurements.<<ETX>>

Self-aligned vertical p-n-p transistor: Device characterization from room to cryogenic temperatures

Abstract High-performance p-n-p transistors have been fabricated utilizing the conventional self-aligned ion-implanted double-polysilicon approach. In the present profile and process design, heat cycle compatibility with the n-p-n transistor process was preserved. Device characteristics from room temperature down to cryogenic temperatures are presented. These transistors operated with high current gains of 47–57 at 300 K and ⩾ 10 at 84 K, respectively. Nearly ideal p-n-junction behavior with very low base leakage was observed over the entire temperature range. Excellent breakdown characteristics were also achieved. Under the active bias mode, no appreciable impact ionization current was detected for base-collector reverse voltage up to 5.25 V at all measurement temperatures. Devices built on this technology are suitable for broad-temperature-range and complementary-circuit applications.