Pong-Fei Lu

Collector-base junction avalanche effects in advanced double-poly self-aligned bipolar transistors

Observation of base-current reversal induced by avalanche multiplication is reported in advanced self-aligned bipolar devices at a collector junction reverse bias less than 3 V. Temperature measurements were carried out to verify the avalanche mechanism, and the dependence on the collector doping profile and high-level injection effects was investigated both experimentally and by numerical simulations. The avalanche effect, which is expected to aggravate with scaling, will eventually threaten normal circuit operation if certain criteria for base-collector reverse bias cannot be maintained. >

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

A submicrometer high-performance bipolar technology

The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated.<<ETX>>

Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology

The authors have developed a planar, self-aligned, epitaxial Si or SiGe-base bipolar technology and explored intrinsic profile design leverage for high-performance devices in three distinct areas: transit time reduction, collector-base (CB) junction engineering, and emitter-base (EB) junction engineering. High f/sub T/ Si (30-50 GHz) and SiGe (50-70 GHz) epi-base devices were integrated with trench isolation and polysilicon load resistors to evaluate ECL (emitter coupled logic) circuit performance. A 15% enhancement in ECL circuit performance was observed for SiGe relative to Si devices with similar base doping profiles in a given device layout. Minimum SiGe-base ECL gate delays of 24.6 ps (8 mW) were obtained. Lightly doped spacers were positioned in both the EB and CB junctions to tailor junction characteristics (leakage, tunneling, and avalanche breakdown), reduce junction capacitances, and thereby obtain an overall performance improvement.<<ETX>>

Low‐frequency noise in self‐aligned bipolar transistors

We report the first study of the low‐frequency noise in self‐aligned npn bipolar transistors, which use the polysilicon emitter. Some of these devices showed excess noise spectra different from the 1/f law generally observed in diffused junction transistors, and the spectral shape S( f ) was found to vary from sample to sample. For instance, we have observed two different characteristics, S( f )∼1/f and S( f )∼1/[1+( f/f0)2], in two adjacent transistors on the same chip. We attribute the latter to carrier trapping in the oxide barrier at the poly‐/monosilicon boundary, whose inhomogeneity could explain the wide variation of the noise spectra.

A reduced-field design concept for high-performance bipolar transistors

A device profile design concept that reduces the junction field, and thus the high-field induced leakage currents as well as the avalanche current, is described. The insertion of an i-layer of thickness equal to the depletion-layer width of the original n/sup +/-p/sup +/ junction can lower the junction field by about a factor of two. Computer studies show that using this design, the collector avalanche current can be reduced by more than one order, while compromising little in the switching speed of the transistor.<<ETX>>

A semi-custom design flow in high-performance microprocessor design

In this paper we present techniques shown to significantly enhance the custom circuit design process typical of high-performance microprocessors. This methodology combines flexible custom circuit design with automated tuning and physical design tools to provide new opportunities to optimized design throughout the development cycle.

Low-temperature avalanche multiplication in the collector-base junction of advanced n-p-n transistors

The collector-base junction avalanche in advanced n-p-n transistors in the temperature range of 293 to 83 K is described. The multiplication factor is shown to increase exponentially with decreasing temperature. The dependence decreases with increased collector doping concentration and, for the same device, with increased reverse bias. At a fixed collector bias, it is roughly constant at low current density, but varies with I/sub c/ at high-level injection due to space-charge modulation. Measurements at low temperatures excluded self-heating in the devices, and it was possible to study high-level injection effects at collector current densities higher than 10 mA/ mu m/sup 2/. Extensive computer simulations were performed to study the effects of the field and carrier distributions. It was observed that, at very high current densities, when the injected carrier density in the collector junction exceeds 1*10/sup 17/ cm/sup -3/, there is an anomalous drop in the avalanche multiplication rate that conventional device simulators fail to predict. The latter is attributed to electron-electron scattering that retards impact ionization by quickly redistributing the excess energy through interparticle collisions. >

A dynamic body discharge technique for SOI circuit applications

It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.

On-Chip circuit for monitoring frequency degradation due to NBTI

This work describes the design and characterization of a unique circuit which can be easily integrated into a microprocessor product in order to determine the degradation of circuit speed caused by negative bias temperature instability (NBTI)-induced shifts under typical product operating voltage and temperature. These data can subsequently be compared to models for circuit degradation in order to assess the validity of the models.