Louis Lu-Chen Hsu

Fuse processing using dielectric planarization pillars

Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure

Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD

High-density dram structure on SOI

Self-trimming method on looped patterns

Method of making a high-density DRAM structure on SOI

Mixed memory integration with NVRAM, dram and sram cell structures on same substrate

Device and method for fabricating double-sided SOI wafer scale package with optical through via connections

Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure

Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation