Katsuhiro Shimohigashi

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic

A 3.8-ns, 257-mW, 16*16-b CMOS multiplier with a supply voltage of 4 V is described. A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality. Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 2.6 ns with 60 mW at 77 K. >

An experimental large-capacity semiconductor file memory using 16-levels/cell storage

In recent years, high density and high speed file memories have become increasingly important for achieving higher performance in computer systems. Multilevel storage dynamic memories offer advantages in terms of speed and density for file usage. An experimental 4Mbit memory has been designed and fabricated utilizing a newly developed multilevel storage scheme and unique peripheral circuits. These include a staircase pulse generator for multilevel storage operation, a voltage regulator for maintaining storage level accuracy, an error correcting circuit for protecting the data from alpha-particle-induced soft error, and a timing generator for testing the device as a fully integrated LSI memory.

A 3.8 ns CMOS 16atimes;16 multiplier using complementary pass transistor logic

A 3.8-ns, 257-mW CMOS 16×16 multiplier with a supply voltage of 4 V is described. A complementary pass transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary input/output, an NMOS-pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as the conventional CMOS due to lower input capacitance and greater logic construction ability. Its multiplication time is believed to be the fastest ever reported, even including times of bipolar and GaAs ICs, and it is shown to be further enhanced to 2.6 ns and 60 mW at 77 K

0.1 mu m CMOS devices using low-impurity-channel transistors (LICT)

Summary form only given. It was found that LICTs are very effective for providing low threshold voltages with good turn-offs in 0.1 mu m CMOS devices. Attention is given to device fabrication criteria, key process technologies used, and the features achieved using LICTs.<<ETX>>

A 25 mu m/sup 2/, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity

A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers retention voltage to less than 0.5 V and the soft error rate (SER) under high-speed operation by about an order of magnitude. A 5-fF cross-coupled capacitor improves the retention mode SER by more than an order of magnitude and low standby power is attained with a 0.1-pA OFF current of the poly-Si PMOS. The performance has been evaluated using a 4-kbit SRAM. The cell area has been reduced to 25.38 mu m/sup 2/ using half-micron CMOS technology.<<ETX>>

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAMs is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty.

Low-voltage ULSI design

An overall view on low-voltage device and circuit design is presented, beginning with a discussion of the low-voltage limit. Low-voltage device design is then described. Low-voltage CMOS and BiCMOS logic circuits are discussed. Circuit techniques for the low-voltage DRAMs and SRAMs are presented. The low-voltage analog devices and circuits are considered. The future direction of the low-voltage and low-power ULSIs is discussed by comparing the switching energy of electronic devices and brain cells. >

Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's)

0.1- mu m CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135 mu m, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICTs suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings.<<ETX>>

Short-channel MOSFET's in the punchthrough current mode

Results of two-dimensional device analysis are compared with experiment for 0.8-µm Si-gate ion-implanted MOS devices operated under conditions of punchthrough transport. Characterization of the punchthrough mode of device operation (a critical factor which limits the maximum drain voltage of submicron MOS VLSI devices) with experiment and simulation has shown that the observed power-law dependence of I DS versus V_{DS} (V_{GS} = V_{SB} = 0) is related to the drain-induced barrier-height lowering. Results of the simulation show the dependence of the punchthrough current upon the range and maximum doping level of the channel implantation. Increasing the substrate-bias or applying a negative-gate voltage is shown to increase the punchthrough voltage. This simulation, which combines results of the process-simulation program (SUPREM) and device-simulation program (CADDET), is shown to predict the behavior of this mode of operation where previous one-dimensional theory has failed.

An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell

The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5- mu m CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is comparable to that of the conventional high-resistivity polysilicon load cell at a supply voltage of 5 V. The cell stability is also improved using a PPL cell, so that the low-voltage operation is assured. >