Tohru Yamazaki

A 5 ns 1 Mb ECL BiCMOS SRAM

A 1 M-word*1-b emitter-coupled-logic (ECL) SRAM in 0.8- mu m BiCMOS technology that achieves 5-ns access time using (1) wired-OR predecoders, (2) ECL CMOS level converters with partial address decoding, and (3) sensing with small differential voltage swing on long read bus lines is described. The memory cell array is divided into two 512 K-cell subarrays. Each subarray consists of 16 32-kb arrays, each of which is organized into 256 rows and 128 columns. An X-decoder is located between a pair of 32-kb arrays. Address input signals are received by an ECL address buffer. The first circuit for address decoding is a wired-OR predecoder, which does the predecoding and predecoded signal line driving. Predecoded address signals with about 1.2-V voltage swing drive 16.5-mm predecoded lines between two 512-kb subarrays and are received by partial-decoding level converters at corresponding 32-kb arrays.<<ETX>>

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word*1 b/1 M word*4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm*8.77 mm. Memory cell size is 5.8 mu m*3.2 mu m. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55- mu m BiCMOS process technology with a triple-well structure. >

High speed submicron BiCMOS memory

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAMs with 0.8 /spl mu/m, 0.55 /spl mu/m and 0.4 /spl mu/m design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAMs. Future prospects for submicron BiCMOS memories are also forecasted. >

A 5 GHz-band BiCMOS up/down-converter chip for GMSK modulation wireless systems

This multi-functional BiCMOS-based up/down-converter chip operating with a single bias voltage of 2.6-5.2 V developed for 5 GHz-band Gaussian minimum shift keying (GMSK) modulation wireless systems. To achieve these features, the following steps are taken: 1) To realize an independently optimum constant current source for each high-frequency circuit in the chip over a wide dc voltage, a distributed single power-supply arrangement is proposed. 2) To realize an attenuation feature without additional power dissipation and chip area, a low-noise attenuating amplifier concept is suggested. 3) To comply with the GMSK modulation requirement, a high-gain small phase variation limiting amplifier is incorporated. 4) To keep the phase noise and power consumption of the local oscillator (LO) low, a frequency doubling method is employed. The present chip can be combined with a GaAs power amplifier/antenna switch chip to provide a complete 5 GHz front-end system.

A 6 ns 4 Mb ECL I/O BiCMOS SRAM with LV-TTL mask option

The authors report on a 4-Mb BiCMOS SRAM which achieves 6-ns and 8-ns access times with ECL (emitter coupled logic) and TTL (transistor-transistor logic) I/O interfaces, respectively, using: (1) a BinMOS converter directly connecting the ECL level to the CMOS level, (2) a high-speed BinMOS circuit with low-threshold voltage nMOSFETs, (3) an optimum word decoder, and (4) high-speed bipolar sensing circuits with a 3.3-V supply. The SRAM is applicable to either an ECL 100 K interface (VCC=0 V, VEE=4.5 V) or an LV-TTL interface (VCC=3.3 V, VEE=0 V), depending on the mask option used.<<ETX>>

A 0.18-/spl mu/m RF SiGe BiCMOS technology with collector-epi-free double-poly self-aligned HBTs

This paper describes an RF SiGe BiCMOS technology based on a standard 0.18-/spl mu/m CMOS process. This technology has the following key points: 1) A double-poly self-aligned SiGe-HBT is produced by adding a four-mask process to the CMOS process flow-this HBT has an SiGe epitaxial base selectively grown on an epi-free collector; 2) two-step annealing of CMOS source/drain/gate activation is utilized to solve the thermal budget tradeoff between SiGe-HBTs and CMOS; and 3) a robust Ge profile design is studied to improve the thermal stability of the SiGe-base/Si-collector junction. This process yields 73-GHz f/sub T/, 61-GHz f/sub max/ SiGe HBTs without compromising 0.18-/spl mu/m p/sup +//n/sup +/ dual-gate CMOS characteristics.

A BiCMOS 300 ns attack-time AGC amplifier with peak-detect-and-hold feature for high-speed wireless ATM systems

Important issues for AGC amplifiers in burst-transmission-based high speed networks such as wireless ATM are: (1) realization of sub-ms attack-times, (2) ability to detect and trace the maximum level for the preamble sequence signal to adjust the gain for determining the equalizer parameters, and (3) noise performance. To control the amplifier gain, conventional AGC amplifiers utilize a control voltage provided by the digital signal processing (DSP) unit of the system. For this reason, the minimum achievable attack-time and the gain control linearity are affected by the DSP unit and number of control bits. This fully-integrated low noise AGC amplifier includes on-chip peak-detect-and-hold gain control circuitry with short attack-time, developed for IF transceiver applications.

A stacked emitter polysilicon (STEP) bipolar technology for 16 Mb BiCMOS SRAMs

A stacked emitter polysilicon (STEP) bipolar technology is described for megabit BiCMOS static RAMs (SRAMs) using TFT (thin film transistor) load cells. The STEP electrode structure consists of the gate (bottom) and the channel (top) polysilicon layers of the TFT. This technology overcomes the perimeter and plug effects for narrow emitter windows. A tungsten-silicide ground line in the RAM cell can be employed to realize a highly stable cell operation at 3.3 V in a 16-Mb BiCMOS SRAM.<<ETX>>

A 0.15 /spl mu/m/0.6 dB-NF/sub min/ RF BiCMOS technology using cobalt silicide ground shields

This paper describes a newly developed cobalt silicide ground shield without any additional process step for a 0.15 /spl mu/m RF BiCMOS. By using this ground shield, low NF/sub min/ values of 0.6 dB/0.3 dB at 2 GHz with bipolar/nMOS transistors were simultaneously achieved and NF50 of an on-chip spiral inductor was remarkably improved at high frequency.