Masahiro Ichimiya

CMOS open defect detection by supply current test

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results promised that, by using the method, open defects in CMOS ICs can be detected by measuring supply current which flows when time-variable electric field is applied.

High speed IDDQ test and its testability for process variation

A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.

A current sensing circuit for feedback bridging faults

In this paper, a supply current sensing circuit for detecting feedback bridging faults, which generates oscillations when a sensitized input is provided, is proposed. The circuit consists of an I-V transformer, a high-frequency amplifier and a demodulation circuit. It is shown by some experiments that such bridging faults can be detected with the circuit.

I/sub DDQ/ sensing technique for high speed IDDQ testing

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, where the output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I/sub DDQ/ sensor design and external I/sub DDQ/ sensor design. It is shown experimentally that high speed I/sub DDQ/ tests can be realized by using the technique.

A high speed I/sub DDQ/ sensor for low-voltage ICs

A new high speed Built-In Current (BIC) sensor is proposed, which is applicable for I/sub DDQ/ tests of low power ICs. The layout of the sensor is designed with CMOS 1.2 /spl mu/m technology. By using this sensor, resistive bridging faults in a circuit, whose supply voltage is 3.3 V, can be detected at the test speed of 66.7 MHz.

Test pattern for supply current test of open defects by applying time-variable electric field

Test input vectors for a supply current test method are discussed which is used for detecting open defects in CMOS ICs. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at a floating node. To generate excessive supply current by the induced voltage change at the floating node, test pattern must be provided so that a conducting path from V/sub DD/ to GND can be generated in the faulty circuit. In this paper, the requirements are denoted to be satisfied as a test input vector of the test method. Also, it is shown that test pattern of functional tests based on stuck-at fault models can be used for the open defect detection method. Furthermore, the experimental results in this paper promise that high fault coverage can be achieved by applying the subset of the stuck-at test pattern to the detection of open defects.

CMOS open defect detection based on supply current in time-variable electric field and supply voltage application

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable supply voltage and electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results show that, by using the method, open defects in CMOS ICs can be detected. Also, the test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models.

T-Reflex Studies in Human Upper Limb Muscles During Voluntary Contraction: Normative Data and Diagnostic Value for Cervical Radiculopathy

OBJECTIVE To evaluate the diagnostic utility of the T reflexes elicited from the upper limb muscles during standardized volitional contraction monitored by a real-time integrating electromyographic analyzer. DESIGN Prospective descriptive study. SETTING Department of orthopedic surgery at a university hospital. PARTICIPANTS Healthy subjects (n=80) evenly distributed across decades of age from 21 to 79 years, and 12 consecutive patients with a single cervical root lesion based on clinical and magnetic resonance imaging studies and diagnostic block. INTERVENTIONS Not applicable. MAIN OUTCOME MEASURES Using a special hammer, which externally triggers the sweep on skin contact, we evoked T reflexes in the biceps (C5), brachioradialis (C6), triceps (C7), and the first dorsal interosseous muscles (C8). RESULTS Simultaneous regression analyses yielded clinically useful upper limits of normative values for latencies, side-to-side differences, and amplitude ratios adjusted to age and arm span. Comparison of the T reflexes between the 2 sides localized the solitary root lesions with a high sensitivity (92%), specificity (81%), and accuracy (83%). T-reflex studies proved helpful to localize the lesion even in patients who solely complained of upper limb pain. CONCLUSIONS The T reflexes with a standardized facilitation of the upper limb muscles provide a clinically useful, noninvasive measure to localize the C5 to C8 radiculopathies. This study contributes in reassessing the currently underused T reflex as an electrodiagnostic technique.

Electric field for detecting open leads in CMOS logic circuits by supply current testing

Open leads are one type of defect occurring frequently when logic circuits are implemented on printed circuit boards (PCBs) with ICs. A powerful supply current test method has been proposed for detecting an open lead in a CMOS logic circuit. The method is based on the supply current of a circuit under test which flows when a time-varying electric field is supplied from the outside of the circuit. The paper proposes a time-varying electric field which enables us to detect open leads in a CMOS logic circuit with an inexpensive test setup.

Test circuit for CMOS lead open detection by supply current testing under AC electric field application

A test circuit is proposed for detecting lead opens of CMOS ICs by measuring the supply current of a CMOS circuit made of the ICs which flows when AC electric field is applied from the outside. A signal of a sine waveform is provided to the test circuit. In the test circuit, the amplitude of the signal increases in proportion to time during a prespecified time. The amplified signal is provided to electrodes for AC electric field to be supplied to a circuit under test. When supply current change which is larger than a threshold value appears, it stops increasing the amplitude and the test circuit concludes that a lead open occurs in the circuit. If the elevated supply current change does not appear within the specified time, the test circuit concludes that the circuit is fault-free. It is shown by our experiments that lead opens in a CMOS IC is detected with the test circuit.