Hiroyuki Yotsuyanagi

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines

Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).

CMOS open defect detection by supply current test

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results promised that, by using the method, open defects in CMOS ICs can be detected by measuring supply current which flows when time-variable electric field is applied.

Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture

In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments with the prototyped IC and by Spice simulation. The simulation results show that an open defect can be detected within 10nsec which generates only additional delay of 0.7nsec.

High speed IDDQ test and its testability for process variation

A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.

A built-in test circuit for supply current testing of open defects at interconnects in 3D ICs

In this paper, a built-in test circuit is proposed to detect and locate open defects occurring at interconnects between dies in a 3D IC by means of the quiescent supply current. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. Testability of the testing with the test circuit is evaluated by Spice simulation. The simulation results show us that a hard open defect and a soft open one generating additional delay of 0.58nsec can be detected at a test speed of 100MHz.

A Novel Approach for Improving the Quality of Open Fault Diagnosis

With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line.

On configuring scan trees to reduce scan shifts based on a circuit structure

In this paper, a new method for reducing test application time of sequential circuits with scan design is proposed. Scan design is one of most popular design for testability techniques. To reduce scan shifts required to provide the scan pattern, a fully testable scan tree configuration is proposed. The method can configure scan trees before generating test vectors without degrading fault coverage by considering a circuit structure. In a fully testable scan tree, flip-flops are placed in parallel in case that they have no overlap in the set of the outputs connected from them. To reduce much scan shifts, a folding scan tree, which is configured based on a fully testable scan tree by placing more flip-flops in parallel, is also configured. Moreover, a scan tree configuration considering scan-out operation is also presented. Experimental results for benchmark circuits are shown.

Identification of feedback bridging faults with oscillation

When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may be generated in the circuit. In this paper, the necessary conditions are presented for feedback bridging faults to generate logical oscillation. Also, a method is proposed to identify such faults in feedback bridging ones. It is based on piecewise-linearized models obtained from input/output characteristics of logic gates and does not require circuit simulation of large size of circuits to identify them. In the experiments for evaluating the method, all of the feedback bridging faults to generate logical oscillation are identified by using the method.

Undetectable fault removal of sequential circuits based on unreachable states

We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.

A built-in supply current test circuit for pin opens in assembled PCBs

In this paper, a built-in test circuit of electrical tests is proposed to detect pin opens of CMOS ICs. When a circuit is tested by the test method, current is made to flow through a targeted pin. An open defect is detected by means of the difference between the current of a defect-free circuit and the measured one. Feasibility of tests with the built-in supply current test circuit is examined by Spice simulation. It is shown that a pin open in a CMOS IC can be detected with the test circuit at a speed of 1MHz.