Yukiya Miura

On estimation of NBTI-Induced delay degradation

NBTI, which is one of well-known aging phenomena, brings delay degradation in deep submicron VLSIs. In order to detect NBTI-induced delay faults, we need to estimate delay degradation and apply delay test for the circuit in the field. This paper discusses on estimation of NBTI-Induced delay degradation. We first analyze the effect of the delay degradation, and then give a procedure of path selection in which long paths after the delay degradation are selected for the delay test in the filed. Experimental results show that estimation of delay degradation significantly affects path selection, and accurate estimation is important for the test.

DART: Dependable VLSI test architecture and its implementation

Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources.

On-chip temperature and voltage measurement for field testing

This paper proposes a novel technique to measure temperature and voltage on-chip in field test. It consists of three types of NBTI-tolerant ring oscillator and counters constructed with a standard cell library. Temperature and voltage are estimated with high accuracy and in a short time.

An IDDQ sensor circuit for low-voltage ICs

A novel IDDQ sensor circuit with high sensitivity that operates at a low supply voltage is proposed. The circuit does not need an I-V translator but is directly driven by an abnormal IDDQ. The circuit can operate at either 5-V VDD or 3.3-V VDD with the same design. Simulation results show that it can detect a 16-/spl mu/A abnormal IDDQ at 3.3-V VDD and can reduce the voltage drop and performance penalty of the circuit under test.

Real-time current testing for A/D converters

The author has revised current testing for analog circuits, examined his method for effective fault detection, and applied it to an A/D converter. This method measures the integral of the power supply current during one clock period in which a test vector is applied. Simulation results show effective detection of target faults in the CUT when applying a step voltage input and easier detection when applying a higher power supply voltage.

A case study of mixed-signal integrated circuit testing: an application of current testing using the upper limit and the lower limit

Many recent ASICs include both analog and digital circuits, called mixed-signal integral circuits, to realize required functions on one chip. The comparator circuit is a principal element in the mixed-signal integrated circuit. In this paper we discuss a method for testing CMOS comparators. The method is current testing using both the upper limit and the lower limit. Bridging faults and break faults are assumed on the circuit layout and are analyzed by a circuit simulator. We examine the efficiency of fault detection by current testing. The result of the test shows that the proposed testing method has the highly fault coverage more than 94 percent.<<ETX>>

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test

Field test is performed in diverse environments, in which temperature varies across a wide range. As temperature affects a circuit delay greatly, accurate temperature monitors are required. They should be placed at various locations on a chip including hot spots. This paper proposes a flexible ring-oscillator-based monitor that accurately measures voltage as well as temperature at the same time. The measurement accuracy was confirmed by circuit simulation for 180 nm, 90 nm and 45 nm technologies. An experiment using test chips with 180 nm technology shows its feasibility.

I/sub DDQ/ sensing technique for high speed IDDQ testing

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, where the output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I/sub DDQ/ sensor design and external I/sub DDQ/ sensor design. It is shown experimentally that high speed I/sub DDQ/ tests can be realized by using the technique.

A high speed I/sub DDQ/ sensor for low-voltage ICs

A new high speed Built-In Current (BIC) sensor is proposed, which is applicable for I/sub DDQ/ tests of low power ICs. The layout of the sensor is designed with CMOS 1.2 /spl mu/m technology. By using this sensor, resistive bridging faults in a circuit, whose supply voltage is 3.3 V, can be detected at the test speed of 66.7 MHz.

IDDQ testability of flip-flop structures

We describe IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, five kinds of master-slave D-type flip-flops are used as the circuit under test. Target faults are bridging faults. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that faults in some flip-flops cannot be detected by IDDQ testing, and this problem depends on the flip-flop structure. Performances of fully IDDQ testable flip-flops are also examined.