Toshiyuki Okayasu

A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input

An on-chip jitter measurement circuit in 0.18 /spl mu/m CMOS is demonstrated, using a combination of a programmable delay line, interleaving PFD, and programmable charge pumps. The method does not require a reference clock. Interleaving PFD minimizes bias errors. Measurement linearity is 3.5 /spl mu/V/ps with an error of 1.03ps/sub rms/ for a 2GHz clock.

Direct current to 34.1-Gb/s, 19-Gb/s/cm/sup 3/ low-jitter parallel optical interconnecting module for high-speed memory test systems

A protocol-free parallel optical interconnecting module is introduced as a solution to solve memory test system transmission bottlenecks. The optical transmission system flexibly suited for a memory test system is reviewed and discussed. A parallel optical module capable of transmitting from dc to 34.1Gb/s (4.267 Gb/s /spl times/8 ch) has been developed. A data transmission throughput density per unit volume of 19 Gb/s/cm/sup 3/ is achieved. A random jitter of less than 3-ps root-mean-square is also achieved. Furthermore, high-density optical connector, high-density optical fiber cable, fiber guides, and cable management/reinforcement members suited for mechanical requirements of the memory test system have been developed.

1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications

A high-speed high-precision dynamic arbitrary timing generator, fabricated in a 0.18mum CMOS process, for >4GHz ATE applications is demonstrated. It exhibits a maximum operating frequency of 1.066 and 4.266GHz (multiplexed mode), a timing resolution of 1.83ps, an INL of <plusmn4ps excluding the calibration RAM, and a random jitter of <0.7psrms

CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system

This paper presents solutions to realize a high-speed, high-precision CMOS timing generator for a 4.266-Gbps memory test system. In order to realize such a timing generator, we developed a 1.066-GHz CMOS timing generator circuit using a high-speed digital delay locked loop circuit and a high-speed, low-INL fine delay circuit. Consequently, we realized a timing generator with 1/20 the size, 4/9 the power, and frac12 the timing error (INL = 8 ps, total jitter =16.8 ps) compared with a conventional timing generator fabricated by the same CMOS process

34.1 Gbps low jitter, low BER high-speed parallel CMOS interface for interconnections in high-speed memory test system

To solve the transmission bottleneck inside ATE systems, we developed a high-speed parallel CMOS interface macro, which is flexibly applicable to ASICs in ATE systems. The interface macro is capable of providing up to 16 TX and/or RX channels: Moreover, multiple macros can be implemented to one chip. The interface macro is capable of transmitting from DC to 34.1 Gbps (2.13 Gbps/spl times/16 channels). In order to achieve ultra-low BER, we have developed a low-jitter digital delay locked loop circuit as a 4-phase clock source for SerDes circuits. This solution yields 1.5 ps rms of random jitter. The random jitter of this macro is less than one-eighth of the interface using PLL. The eye-opening reaches 0.7UI at BER=10/sup -19/.

Real-time testing method for 16 Gbps 4-PAM signal interface

This paper proposes a method for testing a device with multi-level signal interfaces. This method utilizes multi-level drivers that generate multi-level signals and multi-level comparators that are based on a new concept. The multi-level drivers can test the voltage noise tolerance of a receiver device with multi-level signal interfaces. The multi-level comparators realize real-time functional testing of a multi-level signal with the same number of comparators as a conventional test system, by changing the threshold voltage levels dynamically in response to the expected values of a signal under test. This dynamic threshold comparator concept is suitable for a system testing a high-speed multi-level signal. This method is also scalable for an increase in the number of voltage levels such as 8-PAM and 16-PAM signals. In addition, with the proposed method, the testing of a signal having emphasis/ de-emphasis can be realized, and improved testing of the digital modulation signal such as by QAM can be expected. Experimental results are discussed with a prototype circuit that demonstrates the proposed concept applied to a 16 Gbps 4-PAM Test System. Applications of the proposed method are also discussed.

Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing

A dynamic arbitrary jitter injection method that can be integrated into our high speed and high density CMOS timing generator has been developed. This method makes it possible to inject arbitrary jitter including Periodic Jitter, Random Jitter and Data Dependent Jitter in order to realize flexible SerDes device testing. By this method, furthermore, jitter injection is dynamically and synchronously controllable according to a test pattern. We have implemented our jitter injection method in a prototype chip to demonstrate the concept. The chip includes a 6.5Gb/s timing generator and was fabricated by a 90nm CMOS process. Area and power consumption for each edge including the jitter injection scheme and timing generator are 0.2mm2 and 43.8mW respectively.

2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device

A differential time-to-digital converter (TDC), fabricated in 0.18 mum CMOS process, for source-synchronous device testing is demonstrated. It exhibits a maximum sampling rate of 2.133 GS/s, a variable resolution of 10-40 ps, an infinite measurement range, an INL of 8.5 ps(pk-pk), and a jitter of 18.3 ps(pk-pk). It is available to be applied to the jitter histogram measurement without dead-time because it detects all transition timing continuously. Furthermore, a possible application of this TDC to ADC or DAC is suggested.

Ultra hi-speed pin-electronics and test station using GaAs IC

This paper describes the pin-electronics technique applied in a high speed/high pin count test head which targets testing quarter micron high speed CMOS VLSI devices. The pin-electronics operate up to 1 GHz with the following characteristics; timing error<20 ps, rise/fall time<200 ps, minimum pulse width<500 ps, output voltage range -2.0 V to 3.5 V and output voltage amplitude =3.5 V. This was achieved by reducing to 1/5 the GaAs specific problem of changing gain in the low frequency range. The pin-electronics were implemented as a Driver Comparator Multichip Module in order to achieve a high pin count test head (1280 pins max).

CMOS optical 4-PAM VCSEL driver with modal-dispersion equalizer for 10Gb/s 500m MMF transmission

Data communication over 300m of distance, such as Ethernet standards, where the required data rate per channel reaches 10Gb/s or more, demand optical transmission [1]. Vertical-cavity surface-emitting laser (VCSEL) and multimode optical fiber (MMF) are usually used in such optical transmission systems, because they offer several advantages such as ease of assembly and optical alignment for cost reduction. The modulation frequency of commercial VCSEL devices is limited to approximately 10GHz. To overcome this limitation, solutions are reported in [2, 3]. However, these papers merely describe that the modulation frequency of VCSEL can be extended by equalization. On the other hand, the transmission performance of MMF is generally defined by the product of transmission distance and modulation frequency. In a commercial graded-index (GI) MMF, the transmission performance stays about 500MHz-km due to modal dispersion. In the case of 10Gb/s data transmission, the required bandwidth for transmission medium is 10GHz or more [4]. Therefore, when using these commercial GI MMF, the transmission distance will be limited to 50m. Thus, when several hundred meters of transmission is achieved using MMF [4], the modal dispersion of MMF becomes a rather predominant transmission bottleneck than the use of VCSEL . To overcome this bottleneck, a 4-PAM VCSEL driver with an equalization scheme to compensate the modal dispersion of MMF is described in this paper. The driver is fabricated in 90nm CMOS and achives 10Gb/s 500m 4-PAM transmission using conventional MMF having a 500MHz-km of transmission bandwidth. Using this driver, the transmission distance with 10Gb/s is extended by 10× (5GHz-km).