Masanori Fujibayashi

A parallel vector quantization processor eliminating redundant calculations for real-time motion picture compression

A parallel vector-quantization (VQ) processor has been developed aiming at real-time compression of motion pictures using a 0.35-/spl mu/m triple-metal CMOS technology. The chip employs a new search algorithm for VQ encoding to reduce hardware volume. As a result, the die area of the chip is decreased to only 33% of that of conventional fully parallel design. This chip can handle 2048 template vectors by a single chip and is applicable to real-time compression of 30 frames/s full-color VGA (640/spl times/480 pixels) images. The chip operates at 33 MHz with power dissipation of 790 mW under 2.5-V power supply. A real-time motion picture compression system is demonstrated as an application of the chip. This system can transmit five full-color QVGA (320/spl times/240 pixels) images per second below 64 kb/s.

A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture

A still-image encoder based on vector quantization (VQ) has been developed using 0.35-/spl mu/m triple-metal CMOS technology for encoding a high-resolution still image. The chip employs the needless calculation elimination method and the adaptive resolution VQ (AR-VQ) technique. The needless calculation elimination method can reduce computational cost of VQ encoding to 40% or less of the full-search VQ encoding, while maintaining the accuracy of full-search VQ. AR-VQ realizes a compression ratio of over 1/200 while maintaining image quality. The processor can compress a still image of 1600/spl times/2400 pixels within 1 s and operates at 66 MHz with power dissipation of 660 mW under 2.5-V power supply, which is 1000 times larger performance per unit power dissipation than the software implementation on current PCs.

The Flexible Processor-dynamically reconfigurable logic array for personal-use emulation system

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration data by 30% as compared to conventional Look-Up-Table, is implemented. The chip (3.9/spl times/3.9 mm/sup 2/) fabricated with 0.6 /spl mu/m CMOS technology operates at 33 MHz with 5.0 V power supply.

A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture

We have developed an advanced vector quantization (VQ) encoding hardware for still image encoding systems. By utilizing needless calculation elimination method, computational cost of VQ encoding is reduced to 40% or less, while maintaining the accuracy of full-search VQ. We have also developed a still image compression algorithm based on adaptive resolution VQ (AR-VQ), which realizes compression ratio over 1/200 while maintaining image quality. We have successfully implemented these two technologies into a still image encoding processor. The processor can compress still image of 1600/spl times/2400 pixels within one second, which is 60 times faster than software implementation on current PCs.

A still image encoder based on adaptive resolution vector quantization employing needless calculation elimination architecture

We have developed an advanced vector quantization (VQ) encoding hardware for still image encoding systems. By utilizing needless calculation elimination method, computational cost of VQ encoding is reduced to 40% or less, while maintaining the accuracy of full-search VQ. We have successfully implemented the advanced encoding method and Adaptive resolution VQ (AR-VQ), which realizes compression ratio over 1/200 while maintaining image quality, into a still image encoding processor. The processor can compress still image of 1600 x 2400 pixels within one second, which is 60 times faster than software implementation on current PCs.

The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

A parallel vector quantization processor featuring an efficient search algorithm for real-time motion picture compression

A parallel vector quantization (VQ) processor has been developed aiming at real-time compression of motion pictures using 0.35um CMOS technology. The chip employs a new simple search algorithm for VQ encoding. As a result, the die area of the chip is decreased to 33% of that of conventional fully parallel design. This chip can handle 2048 template vectors by a single chip and is applicable to real-time compression of 30 frames/see full-color VGA (640x480 pixels) images. The chip operates at 33 MHz with power dissipation of 790mW under 2.5V power supply.