Masahiro Konda

A fully-parallel vector quantization processor for real-time motion picture compression

Real-time compression of motion pictures is one of the most important technologies in multimedia. For personal and portable applications, efficient encoding/decoding algorithms that run fast on a simple hardware are in demand. Vector quantization (VQ) has a simple decoding algorithm. An extremely expensive computation required for encoding prevents its widespread use. A fully-parallel VQ processor chip for real-time encoding of motion pictures minimizes clock cycles for a single VQ operation and has a versatile code book.

A parallel vector quantization processor eliminating redundant calculations for real-time motion picture compression

A parallel vector-quantization (VQ) processor has been developed aiming at real-time compression of motion pictures using a 0.35-/spl mu/m triple-metal CMOS technology. The chip employs a new search algorithm for VQ encoding to reduce hardware volume. As a result, the die area of the chip is decreased to only 33% of that of conventional fully parallel design. This chip can handle 2048 template vectors by a single chip and is applicable to real-time compression of 30 frames/s full-color VGA (640/spl times/480 pixels) images. The chip operates at 33 MHz with power dissipation of 790 mW under 2.5-V power supply. A real-time motion picture compression system is demonstrated as an application of the chip. This system can transmit five full-color QVGA (320/spl times/240 pixels) images per second below 64 kb/s.

Advances in neuron-MOS applications

This paper shows how computationally-expensive problems like image processing can be handled in real time with little hardware by neuron-MOS (/spl upsi/MOS) circuit technology. In digital signal processing, real-world data (analog, massive in quantities, low-precision and ambiguous) are A/D converted upon acquisition, including inherent noise and distortion, and then are bit-by-bit computed based on rigorous Boolean algebra. In moving-image processing for instance, this requires extraordinary computational powers of DSPs and MPUs, making real-time response of electronic systems unrealistic. Introduction of analog processing would lessen the difficulty, but cost must be traded off for accuracy. Analog/digital merged computation using /spl upsi/MOS circuits features the flexibility of analog processing but preserving the rigorousness of digital. Highly-parallel analog processing is performed for a large volume of analog input data, that is immediately followed by the binary decision of /spl upsi/MOS gates, resulting in the output of digital codes. Real-world data are directly compressed to digital codes without A/D conversion. The power of this scheme is demonstrated in applications to motion vector search in a few hundred nanoseconds and real-time center-of-mass tracing of a moving object and to building real-time event recognition hardware.

Complementary Metal–Oxide–Silicon Field-Effect-Transistors Featuring Atomically Flat Gate Insulator Film/Silicon Interface

In this paper, we demonstrate newly developed process technology to fabricate complementary metal–oxide–silicon field-effect transistors (CMOSFETs) having atomically flat gate insulator film/silicon interface on (100) orientated silicon surface. They include 1,200 °C ultraclean argon ambient annealing technology for surface atomically flattening and radical oxidation technology for device isolation, flatness recovery after ion implantation, and gate insulator formation. The fabricated CMOSFET with atomically flat interface exhibit very high current drivability such as 923 and 538 µA/µm for n-channel MOSFET (nMOS) and p-channel MOSFET (pMOS) at gate length of 100 nm when combined with very low resistance source and drain contacts, four orders of magnitude lower 1/ f noise characteristics when combined with damage free plasma processes, and one decade longer time dependent dielectric breakdown (TDDB) lifetime in comparison to devices with a conventional flatness. The developed technology effectively improves the performance of the silicon-based CMOS large-scale integrated circuits (LSI).

Neuron-MOS correlator based on Manhattan distance computation for event recognition hardware

A minimum-distance-vector fully-parallel-search hardware has been developed based on neuron-MOS (/spl nu/MOS) technology for use in real-time event recognition system. The distance calculation as well as the minimum distance search are conducted based on the voltage-mode operation principle of /spl nu/MOS circuitry, thus enabling fast operation under relatively low power operation. The circuit operation has been demonstrated by HSPICE simulation and test circuits fabricated by a double-poly CMOS process with 3-/spl mu/m layout rules.

A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture

A still-image encoder based on vector quantization (VQ) has been developed using 0.35-/spl mu/m triple-metal CMOS technology for encoding a high-resolution still image. The chip employs the needless calculation elimination method and the adaptive resolution VQ (AR-VQ) technique. The needless calculation elimination method can reduce computational cost of VQ encoding to 40% or less of the full-search VQ encoding, while maintaining the accuracy of full-search VQ. AR-VQ realizes a compression ratio of over 1/200 while maintaining image quality. The processor can compress a still image of 1600/spl times/2400 pixels within 1 s and operates at 66 MHz with power dissipation of 660 mW under 2.5-V power supply, which is 1000 times larger performance per unit power dissipation than the software implementation on current PCs.

Still Image Compression with Adaptive Resolution Vector Quantization Technique

Abstract A novel image compression algorithm based on vector quantization (VQ) technique is proposed in this paper. Adaptive resolution VQ (AR-VQ) method, which is composed of three key techniques, i.e., the edge detection, the resolution conversion, and the block alteration, can realize much superior compression performance than the JPEG and the JPEG-2000. On the compression of the XGA (1024x768 pixels) images including text, for instance, there exist an overwhelming performance difference of 5 to 40 dB in compressed image quality. In addition, we propose a systematic codebook design method of 4x4 and 2x2 pixel blocks for AR-VQ without using learning sequences. According to the method, the codebook can be applied to all kinds of images and exhibits equivalent compression performance to the specific codebooks created individually by conventional learning method using corresponding images.

A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression

A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new architecture of distance calculation unit. By adopting the pipeline composition of each element, the number of distance calculation units could be reduced compared with fully parallel hardware architecture. Besides, in order to reduce memory size of codebook, 2048 template vectors consist of 512 basic template vectors, and the distance calculation units using pipeline composition are arranged in parallel for rotated template vectors. As a result, real-time VQ processor on FPGA is balanced architecture compared with the fully parallel architecture.

Still image compression with mean-residual domain adaptive resolution vector quantization technique

Abstract With the glowing importance of an advanced image processing methods for digital image, an efficient compression algorithm is increasingly important. In this paper we present progressive image compression algorithm based on Vector Quantization (VQ). Mean-Residual domain Adaptive Resolution Vector Quantization technique (MAR-VQ) that combines the adaptive resolution method with the mean-residual method has been developed. The adaptive resolution method changes the resolution of image adaptively according to the form of a pixel block texture in order to increase the performance of compound image compression. In addition, the mean-residual method was introduced as one of the additional techniques to increase continuous-tone image quality by VQ. As a result, MAR-VQ can realize much superior compression performance than the worldwide standard JPEG 2000.

Neuron-MOS-based association hardware for real-time event recognition

Neuron MOS transistor (/spl upsi/MOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in the past memory to the current event based on Manhattan distance calculation and the minimum distance search by a winner take all (WTA) circuitry in a fully parallel architecture. A unique floating-gate analog EEPROM technology has been developed to build a vast memory system storing the events in the past. Test circuits of key subsystems were fabricated by a double-polysilicon CMOS process and their operation was verified by measurements as well as by simulation. As a simple application of the basic architecture, a motion-vector-search hardware was designed and fabricated. The circuit can find out the two-dimensional motion vector in about 150 nsec by a very simple circuitry.