Masanori Furuta

A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters

A wide dynamic range CMOS image sensor with a burst readout multiple exposure method is proposed. In this method, maximally four different exposure-time signals are read out in one frame. To achieve the high-speed readout, a compact cyclic analog-to-digital converter (ADC) with noise canceling function is proposed and arrays of the cyclic ADCs are integrated at the column. A prototype wide dynamic range CMOS image sensor has been developed with 0.25-/spl mu/m 1-poly 4-metal CMOS image sensor technology. The dynamic range is expanded maximally by a factor of 1791 compared to the case of single exposure. The dynamic range is measured to be 19.8 bit or 119 dB. The 12-bit ADC integrated at the column of the CMOS image sensor has DNL of +0.2/-0.8 LSB.

A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB

A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture

A 10-b 30-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is described. The ADC using a pseudodifferential architecture and a capacitor cross-coupled sample-and-hold stage consumes 16 mW with a single 2-V supply. The chip is fabricated in a standard 0.3-/spl mu/m two-poly three-metal CMOS technology. The achieved low-power dissipation normalized by the sampling frequency of 0.52 mW/MHz is superior to other high-speed low-power ADCs reported. The ADC has a signal-to-noise-and-distortion ratio of 54 dB at an input frequency of 15 MHz. The maximum differential and integral nonlinearity are 0.4 and 0.5 LSB, respectively.

A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques

This paper presents a low-power low-voltage 10-bit 100-MSample/s pipeline analog-to-digital converter (ADC) using capacitance coupling techniques. A capacitance coupling sample-and-hold stage achieves high SFDR with 1.0-V supply voltage at a high sampling rate. A capacitance coupling folded-cascode amplifier effectively saves the power consumption of the gain stages of the ADC in a 90-nm digital CMOS technology. The SNDR and the SFDR are 55.3 dB and 71.5 dB, respectively, and the power consumption is 33 mW

A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

This paper presents a high-speed CMOS image sensor with on-chip parallel image compression circuits. The chip consists of a pixel array, an A/D converter array with noise canceling function and an image compression processing element array and buffer memories. The image compression processing element is implemented with a 4times4 point discreate cosine transform(DCT) and a modified zigzag scanner with 4 blocks. A prototype high-speed CMOS image sensor integrating the image compression circuits is implemented based on 1-poly 5-metal 0.25-mum CMOS technology. Image encoding using the implemented parallel image compression circuits to the image captured by the high-speed image sensor is successfully performed at 3,000[frame/s].

A 75mW 10bit 120MSample/s parallel pipeline ADC

This paper describes a low-power high-speed parallel pipeline ADC. The thorough use of digital calibration and the pseudo-differential pipeline ADC architecture allow to realize the low-power design of high-speed ADCs. Capacitor mismatch, gain and offset errors are measured by technique using INL plot, without any modification to ADC core. A prototype ADC with the error correction logic is fabricated in 0.3/spl mu/ 2-poly 3-metal CMOS technology. The 10bit 120M sample/s ADC achieves 0.14LSB of DNL and 0.8LSB of INL with very low power dissipation of 75mW at 2V.

Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits

The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.

A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique

A pre-charging technique to improve the settling response of pipeline stages is demonstrated in a Mbit pipeline A/D converter (ADC). The prototype ADC fabricated in a 0.25 mum CMOS process consumes 102 mW at 30 MSample/s. Measured SNDR and SFDR are 70.7 dB and 82.8 dB, respectively.

A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors

A cyclic analog-to-digital converter (ADC) with pixel noise and column-wise offset canceling for CMOS image sensors is presented. By adding cross connection switches to a cyclic ADC, a column-wise fixed pattern noise due to the amplifiers offset variations is greatly reduced. The proposed ADC also acts as a pixel noise canceller The ADC is optimized with respect to area and power consumption in order to allow the integration of a parallel array at the column of the image sensors. A prototype 12-bit cyclic ADC implemented using a 0.25 /spl mu/m CMOS technology exhibits a 4LSB maximum integral nonlinearity (INL) and 0.9LSB maximum differential non-linearity (DNL) without calibration and 1.5mVp-p column-wise offset deviation. The ADC has 62dB signal-to-noise ratio at 1 Msample/s. The power dissipation is 0.43mW at 3.3V supplies, and the area of one channel is 0.04 /spl times/ 1.2mm/sup 2/.

A 3500fps High-Speed CMOS Image Sensor with 12b Column-Parallel Cyclic A/D Converters

This paper presents a high-speed CMOS image sensor with a global electronic shutter and 12b column parallel cyclic A/D converters. The fabricated chip in 0.25mum CMOS imager technology achieves the full frame rate in excess of 3500 frames per second. The in-pixel charge amplifier achieves the optical sensitivity of 19.9V/lx middot s and the dynamic range of 60dB