Kazutaka Honda

A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques

This paper presents a low-power low-voltage 10-bit 100-MSample/s pipeline analog-to-digital converter (ADC) using capacitance coupling techniques. A capacitance coupling sample-and-hold stage achieves high SFDR with 1.0-V supply voltage at a high sampling rate. A capacitance coupling folded-cascode amplifier effectively saves the power consumption of the gain stages of the ADC in a 90-nm digital CMOS technology. The SNDR and the SFDR are 55.3 dB and 71.5 dB, respectively, and the power consumption is 33 mW

A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique

A pre-charging technique to improve the settling response of pipeline stages is demonstrated in a Mbit pipeline A/D converter (ADC). The prototype ADC fabricated in a 0.25 mum CMOS process consumes 102 mW at 30 MSample/s. Measured SNDR and SFDR are 70.7 dB and 82.8 dB, respectively.

A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers

A 15 b power-efficient pipeline A/D converter using capacitance-coupling non-slewing amplifiers is presented. A modified 1.5b/stage transfer curve combined with the non-slewing amplifier is useful for the error corrections of incomplete settling error. The relationship between the input signal and the incomplete settling errors can be linearized and the errors can be corrected in digital domain with a simple calculation. A prototype ADC fabricated in 0.25 mum process consumes 123 mW at 30 MSample/s and 2.5 V power supply. The SNDR and the SFDR at 30 MS/s are 75.0 dB and 86.5 dB, respectively with the incomplete settling error corrections.

Timing Error Calibration in Time-Interleaved ADC by Sampling Clock Phase Adjustment

Timing error between sampling and holding (SZH) channels for Time-interleaved analog-to-digital converts (TiADCs) is caused by clock skew and RC (sampling resistance and capacitance) mismatch. This paper presents the measurement results of a prototype chip based on our previous work (Z. Liu et al., 2006), in which we showed timing error due to clock skew and RC mismatch can be calibrated simultaneously by adjusting the clock phase. The results show that the residue timing error can be reduce to 1-ps.

A 1V 30mW 10b 100MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques

A 10b 100MSample/s pipeline A/D converter in 90nm process consumes 30mW at 1.0V power supply. The proposed capacitance coupling S/H stage and capacitance coupled class-AB amplifier achieve low distortion and low power dissipation at high-speed sampling. The SNDR and SFDR at 100MHz sampling are 54.0 dB and 70.0 dB, respectively

A New Calibration Method for Sampling Clock Skew in Time-interleaved ADC

A sampling clock skew calibration method with a new calibration signal addition circuit is presented in this paper. The clock skew is detected using a calibration signal, and the calibration is done by adjustment of sample clock delay. The new calibration signal addition circuit consisting of small capacitors and a few switches has little interference to the input signal, and makes it possible for the proposed calibration method to operate at background.

A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues

This paper describes a low-power low-distortion pipeline ADC with 1.0V supply voltage. A cascade amp-sharing architecture and capacitor coupling class-AB amplifier are proposed for low-power dissipation under high-speed sampling. The capacitance coupling S/H stage suppresses the distortion caused by the insufficient gate-source voltage of sampling switches due to a low supply voltage. According to H-SPICE simulation results, the 10b 125MSample/s ADC in 90nm digital CMOS process achieves SNDR of 56dB with a power dissipation of only 21mW