Masanori Tsukamoto

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

Novel channel-stress enhancement technology on damascene gate process with eSiGe S/D for pFET is demonstrated. It is found for the first time that the damascene gate process featured by the dummy gate removal is more effective in increasing channel strain than the gate-1st process as an embedded SiGe stressor technique is used. Furthermore, an additional channel recess related to the damascene process is shown to enhance channel strain, resulting in a 14% Ion improvement at Ioff = 100 nA/um. We propose combining these strain techniques with high-k/metal gate stacks for low-power and high-performance pFETs.

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below

High-Performance Metal/High-

Newly proposed mobility-booster technologies are demonstrated for metal/high-k gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/HfO2 gate stacks with Tinv=1.4 nm on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using HfSix/HfO2 gate stacks with Tinv=1.4 nm. High-performance n- and pFETs are achieved with Ion=1300 and 1000 muA/mum at Ioff =100 nA/mum, Vdd=1.0 V, and a gate length of 40 nm, respectively.

k

A 27nm 16Gb Cu based NV Re-RAM chip has been demonstrated. Novel process introduction to enable this technology include a Damascene Cell, Line-SAC Digit Lines filled with Cu, exhumed-silicided array contacts, raised epitaxial arrays, and high-drive buried access devices.

n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Extreme high-performance n- and pFETs are achieved as 1300 and 1000 uA/um at Ioff = 100 nA/um and Vdd = 1.0 V, respectively, by applying newly proposed booster technologies. The combination of top-cut dual-stress liners and damascene gate remarkably enhances channel stress especially for shorter gate lengths. High-Ion pFETs with compressive stress liners and embedded SiGe source/drain are performed by using ALD-TiN/HfO2 damascene gate stacks with Tinv = 1.4 nm on (100) substrates. On the other hand, nFETs with tensile stress liners are obtained by using HfSix/HfO2 damascene gate stacks with Tinv =1.4 nm.

Process integration of a 27nm, 16Gb Cu ReRAM

A damascene-gate process enhances the drivability in the shorter gate length region, as compared to a conventional gate-first process for pFETs with compressive stress SiN liners and embedded source/drain SiGe. The origin of the gate length effect for damascene-gate pFETs is studied by using UV-Raman spectroscopy and stress simulation. Moreover, the relationship between channel strain and channel width is analyzed, and the enhancement effect of the drivability on channel width is demonstrated. It is found that channel strain is considerably enhanced with the narrower channel width and shorter gate length by the process combination of the damascene gate and stress enhancement techniques. Owing to the enhancement effects of both channel width and gate length, a high drive current of 1090 muA/mum at Vds = Vgs = -1.0 V and Ioff = 100 nA/mum is achieved for the damascene-gate pFET with 0.3-mum channel width and 40-nm gate length.

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

A new symmetric memory cell, in which one wordline is placed at the center, has been developed for 64 Mb SRAM. This new center wordline cell has the benefits of a small cell size, good stability with operation voltages as low as 1.7 V, and suitability for implementation of phase shift lithography. A high performance TFT, which has on/off ratio of 7 orders even at 2.5 V operation, is mounted in this cell.<<ETX>>

Channel-Stress Enhancement Characteristics for Scaled pMOSFETs by Using Damascene Gate With Top-Cut Compressive Stress Liner and eSiGe

An experimental study of mobility and velocity enhancement effects is reported for highly strained short-channel p-channel field-effect transistors (pFETs) using a damascene-gate process on Si (100) and (110) substrates. The relationship between the mobility and the saturation velocity of hole under a compressive stress over 2.0 GPa is discussed. The local channel stress of 2.4 GPa is successfully measured with ultraviolet-Raman spectroscopy for the 30-nm-gate-length device with top-cut compressive-stress SiN liner and embedded SiGe. Mobility and saturation-velocity enhancements of (100) substrate are larger than those of (110) under the high channel stress. In consequence, the saturation current on (100) is larger than that on (110) for the pFETs with higher channel stress and shorter gate length. Moreover, the large enhancement rate of saturation velocity to mobility by the uniaxial stress suggests high injection velocity for the pFETs with the stressors since the high channel stress is induced near the potential peak of the source by using the damascene-gate technology.

Center wordline cell: A new symmetric layout cell for 64 Mb SRAM

Damascene gate process enhances the drivability in shorter gate length region, as compared to conventional gate 1st process for pFETs with compressive stress SiN liner and embedded SiGe. The origin of the gate length effect is investigated for the first time by using the UV-Raman spectroscopy. Moreover, the relationship between channel strain and gate width for damascene gate pFETs is analyzed and the effect is also demonstrated. It is found that channel strain is considerably enhanced in shorter gate length and narrower gate width by the combination of damascene gate process and stress enhancement techniques.

Mobility and Velocity Enhancement Effects of High Uniaxial Stress on Si (100) and (110) Substrates for Short-Channel pFETs

This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the gate length at the edge of the channel beside the shallow trench isolation. In consequence of a mobility boost due to the high tensile stress, drain-current enhancement in the saturation is achieved for the damascene-gate nFETs with the narrow channel width and short gate length.