Masao Yamawaki

A pixel size shrinkage of amplified MOS imager with two-line mixing

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-/spl mu/m CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 /spl mu/A/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)/spl times/5.6 (V) /spl mu/m/sup 2/. Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively.

A 1" format 1.5 M pixel IT-CCD image sensor for an HDTV camera system

A 1-in. format 1.5-million pixel IT (interline transfer) CCD (charge coupled device) image sensor has been developed for an HDTV (high-definition television) camera system. To achieve a low smear ratio while maintaining a high level of sensitivity, the authors have developed a new impurity profile of a buried P/sup +/-layer and an on chip microlens array whose material is a deep-UV resist. Using this sensor, a high-fidelity picture with a horizontal resolution of 820 TV lines has been obtained. The IT-CCD sensor has achieved a smear ratio of less than -90 dB, a sensitivity level of 80 nA/Lx, and a maximum charge handling capacity of 1.2*10/sup 5/ electrons. >

An 0.8-/spl mu/m high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI

A novel lateral power device, termed a p-channel dual-action device (p-ch DAD), is proposed and experimentally demonstrated in action. This device is based on a new dual-action mechanism. The new device has successfully increased on-state current without lowering the device breakdown voltage. The 600-V level-shifting action of the p-ch DAD has been confirmed by a circuit experiment. A newly designed p-ch DAD on the silicon on insulator can be made by adding four additional masks and trench technology to a 0.8-/spl mu/m CMOS process. Moreover, the process we have developed is completely compatible with an existing 5-V 0.8-/spl mu/m CMOS process.

Expression of worst case using multivariate analysis in MOSFET model parameters

Device and circuit performance such as drain current and delay time varies stochastically due to uncontrollable factors in the fabrication processes. In this paper, a new method that represents the variation of the performance as worst case parameters in a MOSFET model is proposed. The variation of the performance can be expressed as a linear combination of several process-related parameters of the MOSFET model. Because of this fact, the worst case of parameters which corresponds to the worst case of performance can be directly and uniformly determined. Therefore, the calculation time of worst case parameters can be reduced by this method. The worst case parameter sets calculated by this method enable designers to estimate circuit performance variations accurately and easily. The capability of this method is verified in the variation analysis of drain current.

A new phenomenon of p-channel dual action device

A novel lateral power device termed the p-channel dual action device (p-ch DAD) is proposed and demonstrated in action experimentally and numerically. It consists of a p-channel HVMOS, n-channel HVMOS and resistance. This hybrid device has increased on-state current without lowering the device breakdown voltage. The conductivity modulation of the new device is discussed.

A 1 inch Format 1.5M Pixel IT-CCD Image Sensor for an HDTV Camera System.

A one-inch format 1.5 M pixel Interline Transfer (IT) CCD image sensor has been developed for an HDTV camera system. We focused on two areas to achieve a low smear ratio while maintaining high sensitivity. One is the VCCD device structure. By using the device simulator, we have developed a new impurity profile for the buried P+-layer under the VCCD. The other focus area is the optical structure. Considering the incident angle, we simulated the optical path. This simulation helped us determine the size of an optical shield and an onchip microlens made of a deep-UV resist. We have achieved a sensivity of 80 nA/lx, a maximum charge handling capacity of 1.2×105 electrons, and a smear ratio less than-110 dB. A high-fidelity picture with a horizontal resolution of 820 TV lines has been obtained.