Shigeto Maegawa

Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's

A lightly doped drain (LDD) structure was used in a gate-all-around TFT (GAT). This suppresses the leakage current much more than the LDD used in a single-gate TFT (SGT), and the current level of the GAT with the LDD is almost the same as that of the single-gate TFT (SGT) with the LDD keeping the GATs advantage of a high on-current. This is because the LDD effectively relaxes the electric field at the drain edge and reduces the effect of the electric field from the surrounded gate of the GAT. Furthermore, the GAT can suppress individual performance variations. The suppression mechanism of the individual performance variation in a GAT was investigated using a poly-Si TFT simulator. The thinner the channel poly-Si, the smaller the individual performance variation of the TFT. The GAT is more effective in decreasing the individual performance variation for thin channels than the SGT because the GAT can achieve the full depletion of the channel poly-Si with a channel thickness twice as large as the SGT. The GAT is eminently suitable for use in high-density, low-voltage operations, and low-power SRAMs.

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI

We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80°C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1 ns row-access time is achieved and 250 MHz operation can be realized by using 2 bank 8 b-burst mode.

Impact of a vertical /spl Phi/-shape transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond

We propose a Vertical /spl Phi/-shape Transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond. The V/spl Phi/T is a vertical MOSFET whose gate surrounds its channel region like a Greek alphabet /spl Phi/. It is built by penetration of the gate electrode (=word line) which has been formed beforehand. Application of the V/spl Phi/T for DRAM cell brings about cell size reduction to 50% and process simplification of about 10% at least. This is mainly because its bit line contact and the V/spl Phi/T are vertically aligned and storage node contact is eliminated. We have indicated that the V/spl Phi/T is an interesting candidate for the gigabit DRAM in view of size, cost and performance.<<ETX>>

Novel SOI wafer engineering using low stress and high mobility CMOSFET with -channel for embedded RF/analog applications

For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved around 7% by changing the buried oxide (BOX) thickness from 400 nm to 150 nm because the self-heating effect is suppressed, and is improved around 5% by changing the substrate resistivity from 10 /spl Omega/cm to 1000 /spl Omega/cm because the power loss is reduced. In this work, the wafer engineering which consists of 1) <100>-channel, 2) optimization of BOX, and 3) high resistivity substrate, is proposed to improve the RF performance of the CMOSFET.

A C-switch cell for low-voltage and high-density SRAMs

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of /spl mu/A order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 /spl mu/m design rules.

Performance and reliability improvements in poly-Si TFT's by fluorine implantation into gate poly-Si

High-performance and high-reliability TFTs have been obtained using a fluorine ion implantation technique. The fluorine implantation into the gate poly-Si of TFT caused a positive Vth shift, increased the ON current, and decreased the leakage current significantly. Our investigation indicates that the Vth shift originates from negative charges generated in the gate oxide by the fluorine implantation. The improvement of drain current is attributed to fluorine passivation of trap states in the poly-Si and to a modulation of offset potential due to the same negative charges under the offset region. Furthermore, high immunity against the -BT stress and TDDB of the gate oxide was achieved by the fluorine implantation. It is considered that the strong Si-F bonds created by the fluorine implantation raise the stress immunity. >

A capacitorless twin-transistor random access memory (TTRAM) on SOI

We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100ms at 80/spl deg/C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1ns row-access time is achieved and 250MHz operation can be realized by using 2bank 8b-burst mode.

A 0.4 μm Gate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories

We propose a novel thin-film-transistor (TFT) structure named gate-all-around TFT (GAT). Its fabrication process is very simple, in that we realize the gate-all-around structure using only a dummy nitride pattern. The GAT shows high channel conductance and features of shield structure peculiar to the double-gate structure. It can also eliminate an anomalous leakage current which appears in the sub-half-micron regime. Combining this process with sacrifice oxidation of the channel poly-Si, we obtained a GAT whose performance is nearly equal to that of single-crystalline metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the GAT requires only one additional mask layer and no increase in TFT area as compared with the conventional single-gate TFT, it is suitable for a high-density and low-cost static-random-access-memory (SRAM). SRAM cells with this GAT have the potential to exhibit performance equivalent to that of the full-complimentary-MOS (CMOS) cell.

An analytical method of evaluating variation of the threshold voltage shift caused by the negative-bias temperature stress in poly-Si TFTs

The variation of the threshold voltage shift (V/sub th/ shift) caused by negative-bias temperature stress (-BT stress) in poly-crystalline silicon thin-film transistors (poly-Si TFTs) was investigated. Based on the chemical reaction caused by -BT stress at the poly-Si/SiO/sub 2/ interface and the poly-Si grain boundary, an analytical method of evaluating the variation of both the V/sub th/ shift and the initial V/sub th/ was proposed. It was shown from this analysis that the enlargement of the poly-Si grain, using Si/sub 2/H/sub 6/ gas could be a solution for efficient reduction of the easily hydrogenated dangling bonds which resulted in the V/sub th/ shift and suppression of the V/sub th/ shift and its variation. Moreover, it was suggested that there are two kinds of the dangling bonds; one is hydrogenated by hydrogenation and can be dehydrogenated by -BT stress; the other is not hydrogenated and the variation of its density is much smaller than the former.

Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits

It has been demonstrated that field shield (FS) isolation technology can suppress the delay time instability according to the operating frequency. The FS isolation technology has been proposed to fix the body potential without any area penalty in a gate array. In this technology, an FS plate, which is an additional polysilicon gate, is introduced to electrically isolate active regions. The body potential of the SOI MOSFET can be fixed through the SOI layer under the FS plate. The effect of body resistance on the delay time instability was also investigated using device simulation. The simulation showed that although the body potential momentarily falls to a nonsteady level due to capacitive coupling during switching operation, the body potential recovers to a steady level, following the RC law. From the simulation result, a helpful design guideline concerning the body resistance was deduced. This guideline showed that the FS isolation has a superior capability to suppress the frequency-dependent instability for practical deep submicron SOI circuits.