Masatada Horiuchi

Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

We demonstrate a new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications. The back gate is effective not only to increase the drive current by about 20% in active mode but also in reduce the off-current by an order of magnitude in stand-by mode. We have also demonstrated tunable-threshold-voltage technology for devices with metal gates and ion implantation for V/sub th/ control. The target V/sub th/ for low-power applications was achieved by using ion implantation for V/sub th/ control. We propose a 6-transistor SRAM memory cell in which we obtain even more benefit from the new device structure by adding a feedback mechanism. A proposed 6-Tr SRAM memory cell is shown to dramatically improve SNM characteristics at the 65-nm technology nodes, and this effect will also apply at finer nodes.

Three-dimensional solid-phase-epitaxial regrowth from As+-implanted Si

Solid‐phase‐epitaxial (SPE) regrowth from selectively As+‐implanted amorphous Si is analyzed by cross‐sectional transmission electron microscopy. SPE regrowth in the (100) wafers proceeds into both vertical and lateral directions simultaneously. For (111) samples, SPE regrowth in the diagonal direction, i.e., 〈100〉 direction near the mask edge, is dominant. In addition to the end of range defects and projected range defects, in the SPE process, defects of a third type are generated just beneath the implantation mask edge. Differences in mask material which control the applied stress at the mask edge have little influence on edge defect generation. Substrate orientation and mask pattern direction play important roles in the edge defect formation mechanism.

Lattice Defects in High-Dose As Implantation into Localized Si Area

Cross-sectional transmission electron microscopy observations have been carried out to clarify two-dimensional depth distributions of lattice defects generated in high-dose (5×1015 and 2×1016 ions/cm2), 80 and 150 keV As-implanted, and annealed Si through 1.0 and 1.5 µm windows on (100) Si. Amorphous Si (a-Si) layer thicknesses formed by implantation range between projected range, Rp, +(5~6) standards deviation, ΔRp, with a lateral spread of about 0.18 times a-Si thickness under the mask edge. Typical post-annealed, induced defects in such amorphous layers are mask edge defects composed of dislocation lines caused by a complicated process for recovering mask edge amorphous layers, together with commonly observed dislocation loops in high-dose As implantation. Interaction between dislocation loops and knocked-on oxygen atoms is discussed, particularly concerning the elimination or survival of As-rich precipitate-induced dislocation loops.

SOLID-II: High-voltage high-gain kilo-Ångstrom-channel-length CMOSFET's using Silicide with self-aligned ultrashallow (3S) junction

A simple novel pile-up phenomenon which leads to an available layered structure of silicide with self-aligned ultrashallow (3S) junction is described. Heavily piled-up impurity (P or B) layers less than 50 nm deep under refractory metal (Ti, W, or Pd) silicide accomplish excellent p-n junction characteristics. Good ohmic properties are also obtained with contact resistivity less than 4 × 10-6ω cm2independent of substrate concentration. This notable profile can easily be realized when a high dose (≥ 5 × 1015cm-2) of impurity is implanted not through but into the refractory metal without intermixing, and followed by Silicidation. An application of this new phenomenon for a kilo-Ångstrom-channel-length CMOSFET is also proposed and evaluated using two-dimensional numerical simulation. In the advanced device, silicide on lightly doped drain II (SOLID-II), the breakdown voltage and current gain product of kilo-Ångstrom-channel-length MOSFETs with 3S junction can be significantly improved in comparison with those of conventional LDD devices. In the 0.3-µm-channel-length devices, current gain reduction in SOLID-II is less than 10 percent compared with that in the standard device. However, in the LDD more than a 20-percent reduction is unavoidable with the same breakdown voltage of 8.5 V. It is proved that the SOLID-II: structures can be used very effectively as a 0.2-0.5-µm-channel-length CMOSFET operatable with 5-V power supply.

Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface

We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SiN gate dielectrics with oxygen-enriched interface (OI-SiN) to suppress both the gate-leakage current and boron penetration. Consequently, N-MOSFET and P-MOSFET have high drive currents of 0.68 and 0.30 mA//spl mu/m, respectively, with I/sub off/=10 nA//spl mu/m, with an EOT value of 1.4 nm. The record gate delay of 280 fs (3.6 THz), for an N-MOSFET with the gate length of 19 nm, has also been achieved.

BESS: a source structure that fully suppresses the floating body effects in SOI CMOSFETs

The floating body effects in SOI CMOSFETs are fully suppressed by a bipolar embedded source structure (BESS) just beneath the n/sup +/ source junction. In this structure, a recombination center, or collector, is formed based on the solid-phase epitaxial mechanism of the Si-implanted SOI layer. The source-drain breakdown voltage of a device with this structure is the same as that of a bulk device, but with a remarkable improvement in the drain-induced barrier-lowering properties.

FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device

The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor with a floating gate. The p+regions are placed outside the channel area by aligning them with the floating gate and are adjacent to the diffused n+source and/or drain regions. This device can operate in the write/erase modes under low-voltage (12 V) and high-speed (< 1 ms) conditions using only a pair of positive pulses. This is achieved with a novel avalanche transition at the channel corner through a relatively thin (4-6 nm thick) oxide under the open-drain condition.

High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer

An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.

Gate-edge effects on SPE regrowth from As+-implanted Si

Abstract Solid phase epitaxial (SPE) regrowth from selectively As + -implantation-induced amorphous Si is studied. Regrowth dependence on substrate orientations (100) and (111) is clarified using cross-sectional transmission electron microscope (XTEM) analysis. Four gate materials are used: photoresist, poly-Si, silicon dioxide, and silicon nitride. The generation of gate or mask-edge defects strongly depends on the two-dimensional shapes of as-implanted amorphous regions under the gate edge. It depends little on gate materials. When tear-drop shaped or circular amorphous profiles form under the gate edge, defect generation strongly depends on substrate orientations and gate direction. The amorphous regrowth rate in the 〈100〉 direction has an essential role in completely inhibiting such defect formation just under the gate edge.

A new dynamic-threshold SOI device having an embedded resistor and a merged body-bias-control transistor

An embedded resistor just under the source junction and a small subsidiary body-bias-control transistor enables construction of a variable-threshold SOI-MOSFET with a small area penalty and without any limitation on the power-supply voltage. In the primary transistor, this resistor not only controls the body potential to increase the on-current and decrease the off-current under the AC condition, but also eliminates floating-body effects. The inverter delay time with and without a 1 pF load capacitance can be shortened to 55% and 40%, respectively, of that of a bulk device under 1 V operation.