Ryuji Kondo

Scaling Down MNOS Nonvolatile Memory Devices

Scaling down of MNOS nonvolatile memory devices are presented. Knowledge of operating mechanisms of the electrically alterable nonvolatile memory provides guidelines for choosing the proper thickness of the gate insulating films (Si3N4 and SiO2). It is found that writing time of an MNOS device depends on the nitride thickness alone but not on the oxide thickness, while erasing time depends on the thicknesses of both films. A 10-V programmable scaled down MNOS memory device is realized by decreasing nitride thickness from 50 nm to 19.5 nm and keeping oxide thickness almost constant at about 2.1 nm. Experimental devices are shown to be highly reliable, if the Si3N4 is slightly oxidized, resulting in an MONOS structure.

An erase model in double poly-Si gate n-channel FAMOS devices

The existence of a poly-Si control gate in an n-channel FAMOS makes the erase characteristics due to ultraviolet light (UVL) illumination different from those of conventional p-channel FAMOSs without control gates. The difference in erasing times between these two types of FAMOS has been explained by the attenuation of UVL in the control gate. However, it was clarified experimentally and analytically in n-channel FAMOS that UVL is propagated horizontally in an optical guide formed between the control gate and substrate and is then absorbed by the floating poly-Si gate. The absorbed UVL intensity in the floating gate through the proposed optical guide is calculated to be 109times stronger than that transmitted directly through the control gate whose thickness and absorption coefficient are assumed to be 3500 Å and 106cm-1, respectively. The proposed optical guide model is supported in experiments that erase time does not depend on the thickness of the control gate (2400- and 3600-Å devices are compared) and erase time in a device whose optical guides are open only on one side and the other side is covered by the control gate is about 2 times longer than that in a device which has two optical guides open on both sides.

n-channel Si-gate MNOS Device for High Speed EAROM

New technologies for high speed and high performance electrically alterable read-only memories are developed. The memory cell consists of an n-channel silicon gate MNOS device and a switching transistor (two devices per bit). This cell configuration and advanced processing technologies realize high speed, no read-cycle limitations, long data retention and high packing density for n-channel EAROMs when compared to conventional p-channel aluminum gate EAROMs. The features of the new MNOS transistors are investigated and capability of ten year unpowered data storage at 125°C is confirmed. Write and erase times are 100 µs and several ms at 25 V, respectively. A single 5 V 2 k-bit EAROM with complete peripheral circuits is also fabricated. The measured access time is about 100 ns, which is more than five times faster than conventional EAROMs.

Analysis and Experimentation on FIMOS (n-channel FAMOS) Devices

Non-volatile nature of FIMOS (Floating gate Ionization-injection MOS) memory is based on the storage of electrons in the floating gate. This paper analyzes the electron injection efficiency in terms of the impact ionization rate and the peak electric field in the channel. The latter is related to the device parameters such as the acceptor concentration in the channel and the oxide thicknesses. Threshold voltage shifts due to the electron injection were measured on experimental units with varied device parameters under various programming conditions. Qualitative agreements were obtained between the theoretical prediction and experimental results. Thus, the injection model should prove useful in the design of better memory devices.