Jun Nakayama

Advanced Quality in Epitaxial Layer Transfer by Bond and Etch-back of Porous Si.

We report recent qualitative advances in bonding and etch-back of silicon on insulator (SOI) using structure-sensitive selective etching of porous Si. The defect density in the epitaxial layer grown on the porous Si is lowered to 3.5 x 10 2 /cm 2 by raising the H 2 prebake temperature in conjunction with the preinjection technique in which a small amount of Si is supplied during the high-temperature H 2 prebake prior to epitaxial growth. H 2 annealing also gives a smooth SOI surface comparable to the bulk polished wafer. Improved thickness uniformity of ±1.8% is achieved using the single wafer processing epi-reactor. The electrical characteristics are evaluated by fabricating pn-junction diode.

Suppression of Si etching during hydrogen annealing of silicon-on-insulator

Generally, polishing is employed as the final treatment of silicon-on-insulator (SOI) at the expense of SOI thickness reduction, because surface microroughness affects the gate oxide integrity. Hydrogen annealing of SOI wafers (Sato and Yonehara, 1994) was originated to replace the polishing, and was traced by several groups. This novel method is advantageous in that there is no thickness reduction in principle. However, in view of the Si etching during hydrogen annealing, various etching rates have been reported in the literature, leading to the question of how much Si is consumed or how much SOI thickness reduction is suppressed. In this paper, Si etching during hydrogen annealing is investigated by using ELTRAN wafers, which are fabricated by transferring epitaxial layers on porous Si on to handle wafers. The lowest reported etching rate to date is achieved.

Reduction of crystalline defects to 50/cm/sup 2/ in epitaxial layers over porous silicon for ELTRAN/sup R/ process

As the design rules of large scale integrated circuits (LSIs) progress, excellent gate oxide integrity (GOI) is demanded despite the requirement for thinner gate oxides. Crystal originated particles (COPs) are currently reported as killer defects for GOI on Czochralski-silicon (CZ-Si) wafers; however, an epitaxial layer on the CZ substrate gives quite good GOI characteristics because of the significantly small amount of COPs in it. It is expected that the epitaxial layer would be used in silicon-on-insulator (SOI), which is one of the candidates for high speed and low power consumption LSIs. We have already reported the epitaxial layer transfer (ELTRAN) method (Yonehara et al, 1994, and Sato et al, 1995), in which the epitaxial layer on porous Si was transferred on to a handle wafer to form an SOI wafer by bonding and etching back of porous Si with extremely high etching selectivity. In this paper, it is reported that the density of stacking faults, which is the major defect in these wafers, is significantly reduced to 50/cm/sup 2/ by controlling both the porous structure and the prebaking step before growth.

High-quality epitaxial layer transfer (ELTRAN) by bond and etch-back of porous Si

The small thickness variation and the high crystalline quality in the SOI films are required for the large scale integration of devices. BESOI is one of the attractive methods due to its layer thickness versatility and productivity particularly in large-scale wafers. Recently, we have reported a novel BESOI method, in which an epitaxial layer on porous Si is transferred onto another handle wafer by bonding and etching back of porous Si (ELTRAN). The structure difference and the abrupt interface between porous and bulk Si gives the very high etching selectivity (10/sup 4/-10/sup 5/), so that it can replace the dopant-sensitive selective etching in the existing BESOI, and allow high-temperature heat treatments (/spl ges/1100/spl deg/C) both to grow the good epitaxial layer and to increase the bonding strength. In this paper, the high etching selectivity and the resultant SOI thickness uniformity are discussed. The crystalline quality of the SOI layer is evaluated by defect delineate etching and p-n junction diodes.

High resistive ELTRAN/sup (R)/ SOI-Epi/sup TM/ wafers for RF application

We report on highly resistive SOI wafers formed by epitaxial layer transfer (ELTRAN) technology focusing on the final resistivity after formation. The lowering of resistivity in the Si wafer of 200 mm ELTRAN SOI was successfully suppressed by controlling the cleanroom ambient and the location of the bonded interface.