Nobuyuki Ikumi

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size

FBC's Potential of 6F 2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

A 6F2 single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBCs spacers can be optimized for making the SSM as large as 8muA at plusmn 4.5sigma without sacrificing the retention time.

A 128Mb Floating Body RAM(FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell

A 128Mbit FBRAM using the floating body cell (FBC) the size of 0.17mum² (6.24F² with F=0.165mum) was successfully fabricated and a high bit yield (~99.999%) was obtained

An early-completion-detecting ALU for a 1 GHz 64 b datapath

A technique with the advantages of pipelining and pseudo-asynchronous design is used to design a 1 GHz ALU datapath including a register file and bypass circuits. Cycle time is reduced from 1.5 ns to 1 ns. Transistor count is increased by only 23%.

Embedded memory design for a four issue superscaler RISC microprocessor

Design of embedded memories for a 64 bit superscaler RISC microprocessor is described. Since the microprocessor issues four instructions per cycle including two memory operations at a time, very wide bandwidth of the primary caches (2.4 GB/sec) is vital. The chip includes 16 KB instruction cache, 2 KB branch cache, 16 KB dual ported data cache and 384 entry dual ported TLB. Unique scheme of TLB hit check greatly reduces critical path. The chip is fabricated in Toshibas high-speed 0.8 /spl mu/m CMOS technology utilizing triple metal and triple well. The die size is 17.3 mm/spl times/17.3 mm and contains 2.6 million transistors. The chip achieves 75 MHz at 70/spl deg/C and 3.1 V.<<ETX>>