Yoshihisa Kondo

A 320 MFLOPS CMOS floating-point processing unit for superscalar processors

A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 mu m CMOS triple-metal-layer technology on a 61 mm/sup 2/ die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80 MHz clock. Furthermore, the original computation mode, twin single-precision computation, double the peak performance and delivers 320 MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique. >

A 4 GOPS 3 way-VLIW image recognition processor based on a configurable media-processor

A 4 GOPS 3-way VLIW image-recognition processor for an automobile system is based on a configurable media-processor which enables design-time configuration to optimize for a specific application. It uses a 0.25 /spl mu/m CMOS process with a standard-cell design method.

An early-completion-detecting ALU for a 1 GHz 64 b datapath

A technique with the advantages of pipelining and pseudo-asynchronous design is used to design a 1 GHz ALU datapath including a register file and bypass circuits. Cycle time is reduced from 1.5 ns to 1 ns. Transistor count is increased by only 23%.

Embedded memory design for a four issue superscaler RISC microprocessor

Design of embedded memories for a 64 bit superscaler RISC microprocessor is described. Since the microprocessor issues four instructions per cycle including two memory operations at a time, very wide bandwidth of the primary caches (2.4 GB/sec) is vital. The chip includes 16 KB instruction cache, 2 KB branch cache, 16 KB dual ported data cache and 384 entry dual ported TLB. Unique scheme of TLB hit check greatly reduces critical path. The chip is fabricated in Toshibas high-speed 0.8 /spl mu/m CMOS technology utilizing triple metal and triple well. The die size is 17.3 mm/spl times/17.3 mm and contains 2.6 million transistors. The chip achieves 75 MHz at 70/spl deg/C and 3.1 V.<<ETX>>