Masatomi Okabe

Current control buffer for multi switching CMOS SOG

To overcome the noise problem in current sub-micron CMOS sea of gates (SOG), an output buffer circuit for the noise reduction is proposed. A current controlling buffer (CCB) reduces the noise spike down to approximately 1/10 of conventional output buffers. The advantage of CCB is verified by the simultaneous switching of 150 output buffers (12 mA type) on 0.8 mu m 184 K-gate CMOS SOG. The noise reduction rate and transition times of three CCB options are shown. The maximum value of 88% which seems to sufficient for multi switching of over 100 buffers.<<ETX>>

An ECL 5000-gate gate array with 190-ps gate delay

The authors describe an ECL 5000-gate gate array for use in mainframe computers. A modified paired-gate cell is introduced to obtain a high utilization of elements and a high functionality. The appropriate selection of emitter-follower currents is performed to achieve high performance for the LSI. The basic gate delay time is 190 ps/gate at a power dissipation of 2.56 mW/gate by using advanced bipolar transistors. To examine the performance of this gate array, a 16-bit multiplier has been implemented by utilizing the automatic CAD system and mounted on a 148-pin pin-grid array package. The multiplication time is 8.3 ns.

A 400 K-transistor CMOS sea-of-gates array with continuous track allocation

A 0.8- mu m CMOS sea-of-gates (SOG) array with first-level wiring channels perpendicular to transistor rows and 40 0K transistors is integrated on a 6*7-mm/sup 2/ chip. Implementation of a 64-bit multiplier shows 60-percent gate utilization and density of 1410 G/mm/sup 2/. The wiring length of the multiplier is 70 percent of that in a conventional SOG. >

A CMOS sea-of-gates array with continuous track allocation

A macrocell architecture which is suitable for sea-of-gates (SOG) arrays and improves gate density is described. A layout scheme using a novel structure called column macrocell (CMC) implements every macrocell by stacking BCs (basic cells) along the BC column until enough gates are accumulated. In the CMC structure, the first-level wiring runs along the BC column, and the wiring channel width can be adjusted by 1-2 tracks. Therefore just as many tracks as are necessary in a channel are produced by first-level wiring. The effectiveness of the CMC structure is verified by implementing an SOG chip using LDD (lightly doped drain) PMOS and NMOS transistors with 0.8- mu m physical and 0.55- mu m effective gate length. The features of the CMC structure are compared with those of the RMC (row macrocell) structure.<<ETX>>