Takahiko Arakawa

Current control buffer for multi switching CMOS SOG

To overcome the noise problem in current sub-micron CMOS sea of gates (SOG), an output buffer circuit for the noise reduction is proposed. A current controlling buffer (CCB) reduces the noise spike down to approximately 1/10 of conventional output buffers. The advantage of CCB is verified by the simultaneous switching of 150 output buffers (12 mA type) on 0.8 mu m 184 K-gate CMOS SOG. The noise reduction rate and transition times of three CCB options are shown. The maximum value of 88% which seems to sufficient for multi switching of over 100 buffers.<<ETX>>

A 400 K-transistor CMOS sea-of-gates array with continuous track allocation

A 0.8- mu m CMOS sea-of-gates (SOG) array with first-level wiring channels perpendicular to transistor rows and 40 0K transistors is integrated on a 6*7-mm/sup 2/ chip. Implementation of a 64-bit multiplier shows 60-percent gate utilization and density of 1410 G/mm/sup 2/. The wiring length of the multiplier is 70 percent of that in a conventional SOG. >

A CMOS sea-of-gates array with continuous track allocation

A macrocell architecture which is suitable for sea-of-gates (SOG) arrays and improves gate density is described. A layout scheme using a novel structure called column macrocell (CMC) implements every macrocell by stacking BCs (basic cells) along the BC column until enough gates are accumulated. In the CMC structure, the first-level wiring runs along the BC column, and the wiring channel width can be adjusted by 1-2 tracks. Therefore just as many tracks as are necessary in a channel are produced by first-level wiring. The effectiveness of the CMC structure is verified by implementing an SOG chip using LDD (lightly doped drain) PMOS and NMOS transistors with 0.8- mu m physical and 0.55- mu m effective gate length. The features of the CMC structure are compared with those of the RMC (row macrocell) structure.<<ETX>>

A basic-cell buffer 440K-transistor CMOS masterslice

A masterslice containing 437,976 transistors on a 12.7×11.96mm2chip and employing a gate-isolation concept with no fixed routing tracks and no dedicated buffers, will be reported. The masterslice has been fabricated in 1.3μm CMOS technology. A 13MHz facsimile processor has been implemented using this array.

A 540 K-transistor CMOS variable-track masterslice

A basic cell structure of p-n-n (a set of one p-channel and two n-channel resistors) is proposed for the cell of a variable-track masterslice (VTM) in order to increase the utilization of logic gates. The masterslice has 180 K p-channel and 360 K n-channel transistors for logic circuitry; it uses 1-3 /spl mu/m double-metal CMOS technology, and has 60 K equivalent (two-input NAND) gates without channel. A small track increment of six or nine allows fine adjustment of the track count in each routing channel. The gate density in p-n-n VTM has been increased by 10 to 30% over a conventional p-n VTM, where p-n represents CMOS pair transistors.

A 400MHz 183mW microcontroller in body-tied SOI technology

A low-power microcontroller is designed in 0.10/spl mu/m body-tied SOI CMOS technology by reusing existing design resources developed in 0.18/spl mu/m bulk CMOS. Only two new masks are needed for this work. The performance is evaluated by simulations and indicates operation at 400MHz with 183mW dissipation at 0.8V and represents a five-times improvement in power-delay product.

A configurable ROM circuit for use in gate arrays

A double word-line memory ROM (DWM-ROM) for use in gate arrays is described. It allows for an automatic layout by reducing the input pin count in the word lines by using two-step addressing. The advantage of this method has been verified by implementing a 16-bit microprocessor using an 8 K-gate array, based on a gate-isolated cell configuration, employing 1.5-/spl mu/m double-metal CMOS technology. The 16-bit /spl times/ 64-word ROM in the processor saves 30% of the transistor area due to the DWM-ROM.

A 1.5&#181;CMOS gate array with configurable ROM and RAM

The use of 1.5μ CMOS technology to implement a 8000 equivalent gate array with double word line memory addressing on a 9.9×9.8mm2chip will be discussed. Describe, too, will be the implementation and operation of a 16b micro-processor with 1024b ROM and 256b RAM.