Masahiro Hatanaka

Identification of stress-induced leakage current components and the corresponding trap models in SiO/sub 2/ films

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the-current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components.

A 400 K-transistor CMOS sea-of-gates array with continuous track allocation

A 0.8- mu m CMOS sea-of-gates (SOG) array with first-level wiring channels perpendicular to transistor rows and 40 0K transistors is integrated on a 6*7-mm/sup 2/ chip. Implementation of a 64-bit multiplier shows 60-percent gate utilization and density of 1410 G/mm/sup 2/. The wiring length of the multiplier is 70 percent of that in a conventional SOG. >

Identification of stress-induced leakage current components and the corresponding trap models in SiO/sub 2/ films [MOS transistors]

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components.

A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy

A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a supply voltage of -5.2 V. An access time of 7 ns has been obtained. Active 680 mW for ×4 mode. The cell size is 5.4 μm×7.2 μm (38.88 μm2); the die size is 5.46 mm×16.16 mm (88.24 mm2)

A 70ns 256K DRAM with bitline shielding structure

THE DESIGN of DRAMS with the smallest die, the fastest access time and the widest operating margin, has been receiving major attention. This paper will report on the development of a 70ns 256K x l b DRAM, using bitline shielding. The chip, whose die area is 3.6 x 8.4mm2 ( = 30.2mm2), is enclosed in a plastic 16-pin, 300mil dual-in-line package. The open-bitline architecture of the array (Figure 1 ) was chosen to provide improved speed, smaller area and better signal level’. However, non-common mode noise occurs from the coupling of column address lines into the bitlines during the sensing period which accounts for 23% of the chip access time. Figure 2 shows the bitline shielding technique applied to the memory. A third-level polysilicon layer, which is connected to the ground, acts as a shielding plate between the diffused bitlines and aluminum column address lines. This shielding plate absorbs non-common mode noises. The polysilicon is also used as bitline material’ ; Figure 3. The time constant of the bitline is one half that of the diffused equivalent. The third level bitlines and the boosted wordlines serve to transfer the signals from the memory cells to the sense nodes rapidly. Moreover, the Vcc cell plate allows effective use of the small memory cell area (63.5pm) and leads to a storage capacitance 9% larger than a grounded cell plate. Thus, it is possible to transfer the memory cell data faster and more efficiently to the sense node, in spite of the smaller cell and die area. Sensing period of the output preamplifiers has also been improved. As shown in Figure 4, only one set of I /O lines is connected selectively to the preamplifier nodes at a time.

A 70 ns 256K DRAM with bit-line shield

A 256K/spl times/1 dynamic RAM has been developed in a triple-poly, single-metal NMOS technology with a open bit-line architecture. Noncommon-mode noise inherent in the architecture is shielded by a third-level polysilicon plate placed between bit lines and signal lines. The die is 30.2 mm/SUP 2/ and is housed in the standard 300-mil and 16-pin dual-in-line plastic package. The RAM has a worst-case access time of 70 ns. Wire bonding of an extra bonding pad determines whether the RAM is for nibble mode or for page mode; this, it is noted, gives much flexibility to production. Laser repairable redundancy with eight spare columns is implemented for yield enhancement.

A CMOS Dual Port Memory with Serial Read/Write Function for Graphic Systems

As the cost per bit of semiconductor memories and the price of small computer systems continue lowering, personal work stations or computer aided design (CAD) systems come to be used widely. The market for graphic display systems also expands, because interactive operations between users and such systems are unavoidable in personal usage.

A 47ns 64KW × 4b CMOS DRAM with relaxed timing requirements

A 256Kb DRAM which eliminates the positive-going RAS signal edge from the internal timing by a time-out function, will be reported. The access time is 47ns with predecoding, and power dissipation is 115mW at 200ns cycle time.