Masatoshi Arai

High speed 0.1 /spl mu/m dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide

A novel dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide is proposed. This technology suppresses boron penetration for pMOS, while maintaining high current drivability for nMOS with simple process steps. In addition, the drain junction capacitance of nMOS is drastically decreased, compared to a conventional MOSFET with arsenic source/drain. The delay time of CMOS ring oscillator was 28 ps, which is due to low junction capacitance and high current driving capability.

A 0.18 /spl mu/m Ti-salicided p-MOSFET with shallow junctions fabricated by rapid thermal processing in an NH/sub 3/ ambient

This paper reports a 0.18 /spl mu/m Ti-salicided p-MOSFET with shallow junctions fabricated by rapid thermal processing (RTP) in an NH/sub 3/ ambient and low energy boron implantation. It is found that the nitrogen atoms induced by the RTP in an NH/sub 3/ ambient diffuse into the substrate in source/drain regions and suppress the diffusion of boron ions. This new process allows the improved short channel effect in sub-0.2 /spl mu/m regime and the suppression of boron penetration for p-MOSFETs with 4-nm gate oxide. Moreover, this process provides high current drivability due to the low resistance at the silicide/p/sup +/-silicon interface and the low sheet resistance on Ti-silicided source/drain regions.

Nitride Trapping Memory Technology to Realize Flash-Embedded SoC of 65nm and Beyond

Nitride trapping memory technology to realize flash-embedded SoC of 65nm and beyond has been demonstrated for the first time. The device of 0.024 mum2/bit has been fabricated with advanced SoC process, comprising NiSi-salicidation, ultra shallow junction, fine planarization, WL gap-filling and highly reliable Cu/FSG interconnect with very narrow pitch. In-process charging damage has been eliminated by newly developed FEOL-level protection diode.

A novel 0.25 /spl mu/m CMOS technology for 6.82 /spl mu/m/sup 2/ 6-Tr. SRAM cell with elevated trench isolation and line-and-space shaped gates (ETILS)

Miniaturization of SRAM cell size is a key issue for multi-media logic CMOS LSIs, such as DSP and MPEG2 decoders/encoders. Recently, several CMOS technologies realizing small cell size less than 10 /spl mu/m/sup 2/ have been reported, while the previous work by M. Minami et al. (1995) achieved an even smaller cell size of 6.93 /spl mu/m/sup 2/, but this process required two-level local-interconnect. In this paper, a novel 0.25 /spl mu/m CMOS technology is developed by an elevated trench isolation technology and line-and-space shaped gate formation (ETILS). This process allows the smallest cell size of 6.82 /spl mu/m/sup 2/ with simple single-level local-interconnect.