Toshiki Yabu

A new half-micrometer p-channel MOSFET with efficient punchthrough stops

This paper describes design and characteristics of a new half-micrometer buried p-channel MOSFET with efficient punch-through stops. The approach for scaling down the buried p-channel MOSFETs is discussed by using two-dimensional process/device simulations and experimental results. The efficient punchthrough stops have realized high punchthrough resistance in half-micrometer dimensions without increasing the n-well concentration and extreme scaling of channel and source-drain junction depths. Moreover, this p-channel MOSFET shows the breakdown voltage to be as high as 10 V. The fabrication sequence is compatible with the conventional n-channel LDD MOSFETs.

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t/sub RAS/=50 ns (typical) at V/sub cc/=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V/sub SS/ shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4- mu m CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM. >

A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers

A circuit design technique for suppressing asymmetrical characteristics in a high-density DRAM sense amplifier is discussed, and the effect of drain current imbalances between transistor pairs and the sensitivity of the sense amplifier are studied experimentally. A sense amplifier composed of parallel transistor pairs which have a reversed source and drain arrangement on a wafer is capable of suppressing the asymmetry effects to less than 15 mV in a range of submicrometer gate lengths and of reducing the layout area by about 43% compared with the conventional sense amplifier. >

A self-aligned retrograde twin-well structure with buried p/sup +/-layer

A self-aligned retrograde twin-well structure with a buried p/sup +/-layer surrounding the n-well is presented. The retrograde twin well and buried p/sup +/-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n/sup +/-to-p/sup +/ spacing. The present CMOS structure provides high latchup immunity at 1.5- mu m n/sup +/-to-p/sup +/ spacing and good isolation characteristics without additional n- and p-channel stop dopings. >

Influence of asymmetric/symmetric source/drain region on asymmetry and mismatch of CMOSFET's and circuit performance

Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5-/spl mu/m surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated with four ion-implantation methods and designed with a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry in MOSFETs with a one-sided 7/spl deg/-implantation method. The symmetric 7/spl deg//spl times/4-implantation method gives good A&M characteristics of n- and p-MOSFETs with the both layouts. According to the circuit performance of ring oscillators, the ion-implantation method is correlated to supply-current/oscillation-frequency/delay-power product and substrate current. The symmetric 7/spl deg//spl times/4-implantation method is the most preferable in terms of A&M and punchthrough immunity of CMOSFET as well as circuit performance.

Spread-vertical-capacitor cell (SVC) for high-density dRAM's

An advanced three-dimensionally (3-D) stacked-capacitor cell, the spread-vertical-capacitor cell (SVC), was developed. SVC realized a storage capacitance (C/sub s/) of 30 fF with a cell area of 1.8 mu m/sup 2/, a capacitor height of 0.37 mu m, and an equivalent SiO/sub 2/ film thickness of 7 nm for oxide-nitride-oxide (ONO). By extrapolating these results to 256-Mb DRAMs, a C/sub s/ of 24 fF is obtained with a cell area of 0.5 mu m/sup 2/, a capacitor height of 0.4 mu m, and an equivalent SiO/sub 2/ thickness of 5 nm, and these values satisfy the specifications for 256-Mb DRAMs. The low capacitor height of SVC makes possible a fabrication process using ArF excimer laser lithography. >

A novel local interconnect technology (MSD) for high-performance logic LSIs with embedded SRAM

A novel local interconnect/contact technology with a self-aligned Metal-Stacked source/Drain structure (MSD) is proposed. This technology provides a self-aligned contact technology for narrow source/drain opening of 0.2 /spl mu/m width with low parasitic resistance and low junction leakage current level. Excellent cell characteristics with 6.82 /spl mu/m/sup 2/ full-CMOS SRAM have been achieved.

The inverse-narrow-width effect of LOCOS isolated n-MOSFET in a high-concentration p-well

The inverse-narrow-width effect (INWE) of a LOCOS-isolated n-MOSFET formed in high concentration p-wells is described. The threshold behavior is characterized as a function of the concentration of p-well, using experimental data and three-dimensional process/device simulations. In a high-concentration p-well, the devices with a LOCOS isolation show the INWE, which was observed in trench-isolated devices. This effect is enhanced with increase of the p-well concentration. The INWE in the LOCOS-isolated MOSFET is explained by the boron segregation phenomenon during LOCOS process and boron redistribution.<<ETX>>

Spreaded-vertical-capacitor cell (SVC) for beyond 64 Mbit DRAMs

An advanced three-dimensionally (3-D) stacked capacitor cell, SVC, was developed. The SVC shows good electrical characteristics, and it realized a capacitance of 43 fF with a cell area of 1.8 mu m/sup 2/. The uniform formation of the capacitor-dielectric-film (oxide-nitride-oxide film: ONO) on the experimental storage electrode indicates the uniform deposition of the ONO film on all kinds of 3-D storage electrodes including that of the SVC. The SVC is the most promising cell structure for beyond 64 Mbit DRAMs (dynamic RAMs).<<ETX>>

Tunnel Structured Stacked Capacitor Cell (TSSC) with High Reliability for 64 Mbit dRAMs and Formation of Oxide-Nitride-Oxide Film (ONO) on 3-dimensionally (3d) Storage Electrode

We developed a new 3-dimensionally(3d) stacked capacitor structure, a tunnel structured stacked capacitor cell (TSSC), for 64Mbit dRAMs. The TSSC with 2 tunnels realized improved reliability the same as that of the conventional stacked capacitor (STC) and a capacitance of 29 fF with a capacitor height of 0.25 µm because of side-wall electrode formation. The equivalent thickness of SiO2 for the oxide nitride oxide (ONO) is 7.8 nm, and the cell area is 1.8 µm2. The uniformity of the ONO inside the tunnel of the TSSC was confirmed except for the corner of the tunnel, while the thickness of the ONO is slightly greater at the corner. At the corner, the top oxide film of the ONO is slightly thicker than that at the other areas, and accordingly, the shape of the plate electrode at the corner becomes round. These shape effects lead to no generation of the local field concentration at the corner inside the tunnel. They are applied to the other 3d stacked capacitors which have generally been proposed.