Masayuki Ikebe

A Wide-Dynamic-Range Compression Image Sensor With Negative-Feedback Resetting

A CMOS image sensor capable of wide-dynamic-range compression is proposed. This sensor has two main features. It uses a negative-feedback technique to set any intermediate voltage into photodiode (PD) capacitance in the pixel circuit. It also uses a quasi-holding function by resetting the pixel-output voltage into PD capacitance. Dynamic range compression is achieved by individually selecting pixels and by setting an intermediate voltage or performing quasi-holding with respect to each pixel. Output data has a polygon-like form corresponding to a change from high sensitivity to low sensitivity as optical intensity becomes stronger. Experimental results obtained with a chip fabricated using a 0.25-mum CMOS process demonstrate dynamic range compression

A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection

A compact complementary metal-oxide semiconductor (CMOS) circuit for depressing synapses is designed for demonstrating applications of spiking neural networks for contrast-invariant pattern classification and synchrony detection. Although the unit circuit consists of only five minimum-sized transistors, they emulate fundamental properties of depressing synapses. The results of the operations are evaluated by both experiments and simulation program with integrated circuit emphasis (SPICE).

Cellular νMOS Circuits Performing Edge Detection with Difference-of-Gaussian Filters

Aiming at the development of high-speed image processors, we propose a cellular νMOS circuit that performs the processing of edge detection. The proposed circuit uses neuron MOS (νMOS) transistors for analog convolution operations with Gaussian-shaped kernel functions, which makes the circuit organization extremely simple as compared with that of conventional convolution circuits. Performances of the proposed circuit are evaluated by simulation program with integrated circuit emphasis (SPICE). The results show the usefulness of the cellular νMOS circuit in image-processing applications.

60-GHz, 9-µW wake-up receiver for short-range wireless communications

We present an ultra-low power 60-GHz band wake-up receiver (WuRx) designed and fabricated with a 0.18-μm RF CMOS low-cost technology. The WuRx consists of an envelope detector, high-gain baseband amplifier, and clock and data recovery (CDR) circuit. Subthreshold-operated offset-voltage cancellers are used in the detector and baseband amplifier. The envelope detector can operate for an on-off keying (OOK) signal with a low bit-rate baseband and 60-GHz carrier, which is higher than the cutoff frequency (fT) of 0.18-μm MOSFETs. This is because the fT defines the maximum operating bit-rate of the baseband signal. The CDR circuit is composed of a clock recovery circuit using an injection-locked oscillator, short pulse generator, and D-type flip/flop. The fabricated WuRx successfully operates with power consumption of only 9 μW from a 1.5-V supply and a high sensitivity of -68 dBm for a 350-kbit/s OOK signal with a 60-GHz carrier. The CMOS die area is 1.09 mm2. This is the first successful fabrication of a 60-GHz WuRx.

Column parallel single-slope ADC with time to digital converter for CMOS imager

We propose a single-slop ADC with a time to digital converter (TDC) that uses a multi-phase clock. Single-slope ADCs have been used as column parallel ADCs for CMOS image sensors. When the TDC with resolution of n bits is adapted to the ADC, the conversion time is reduced by a factor of 2n. Applying the TDC that uses multi-phase-clock signal reduced the number of circuit elements, achieved consistency between the single-slope ADC and the TDC, and realized robust meta-stability. We designed a 12-bit ADC, which consists of the 3-bit TDC and the 9-bit-single-slope ADC, by using a 0.25-µm CMOS process. Through SPICE simulation, we confirmed our single-slop ADC to be more consistent, have more robust meta-stability, and achieve higher-speed ADC operation at 200-MHz clock than the conventional single-slope ADC. The simulated DNL and INL were ±0.25 LSB and ±0.43 LSB.

O(1) bilateral filtering with low memory usage

We propose a O(1) algorithm for bilateral filter with low memory usage. Bilateral filter can be converted into weighted histogram operation. Applying line buffers of column histograms, we can reduce the number of calculation needed to construct recursive center-weighted local histogram. Also our method have advantage in terms of memory requirements. We used a 2-GHz CPU with our method and achieved one million pixels per 0.5 sec operation and high PSNR over 40 dB without the need for temporary frame buffers or additional instructions (downsampling, SIMD instructions, or multi-thread operations).

BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10–10² and 10²–10⁴ times better than a CPU/GPU/FPGA.

Ultra-wideband silicon on-chip antennas with artificial dielectric layer

On-chip antennas are demanded to further lower the cost of wireless CMOS ICs. We placed an artificial dielectric layer (ADL) between an antenna and Si substrate to improve the antenna gain. A 3.1-10.6-GHz ultra-wideband inverted-F antenna with ADL as well as a low-noise amplifier were designed and fabricated using a 0.18-µm mixed signal/RF CMOS process with one poly and six metal layers. A fairly good agreement between measured and calculated gain characteristics was obtained. Using the ADL achieved a 2-dB gain enhancement. Increasing the surface dielectric constant for the ADL is expected to further enhance gain.

Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer

This paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface, we also worked on resolving another throughput-limiter, namely power consuming TDC used in column parallel ADCs. Novel intermittent TDC operation scheme presented in this paper can reduce its power dissipation 57% from conventional ones.

Accuracy improvement of histogram-based image filtering

We propose a method for improving the accuracy of histogram-based image filtering. With this method, we define a histogram called intensity-stacked histogram. An image histogram generally consists of a frequency (number of pixels) for each bin. On the other hand, intensity-stacked histogram stores the sum of intensity values for each bin. The intensity-stacked histogram can be calculated in constant time similar to a standard histogram. We apply the intensity-stacked histogram to histogram-based image algorithms for median and bilateral filters. The histogram-based image filter with the intensity-stacked histogram works effectively when using a few bins. We confirmed that the accuracy of histogram-based image filters using intensity-stacked histogram is higher than that using standard histogram.