Yoshihito Amemiya

A 300 nW, 15 ppm/

A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.

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The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for logic circuits of NAND, NOR, exclusive-OR, and AND-OR combinational logic. Computer simulation shows that the designed circuits perform the logic operations correctly.

C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

This paper proposes an all-analog neural network LSI architecture and a new learning procedure called contrastive backpropagation learning. In analog neural LSIs with on-chip backpropagation learning, inevitable offset errors that arise in the learning circuits seriously degrade the learning performance. Using the learning procedure proposed here, offset errors are canceled to a large extent and the effect of offset errors on the learning performance is minimized. This paper also describes a prototype LSI with 9 neurons and 81 synapses based on the proposed architecture which is capable of continuous neuron-state and continuous-time operation because of its fully analog and fully parallel property. Therefore, an analog neural system made by combining LSIs with feedback connections is promising for implementing continuous-time models of recurrent networks with real-time learning. >

Single-electron logic device based on the binary decision diagram

We describe a majority-logic gate device suitable for use in developing single-electron integrated circuits. The device consists of a capacitor array for input summation and an irreversible single-electron box for threshold operation. It accepts three binary inputs and produces a corresponding output, a complementary majority-logic output, by using the change in its tunneling threshold caused by the input signals; it produces a logical 1 output if two or three of the inputs are logical 0 and a logical 0 output if two or three of the inputs are logical 1. We combined several of these gate devices to form subsystems, a shift register and a full adder, and confirmed their operation by computer simulation. The gate device is simple in structure and powerful in terms of implementing digital functions with a small number of devices. These superior features will enable the device to contribute to the development of single-electron integrated circuits.

An all-analog expandable neural network LSI with on-chip backpropagation learning

This paper proposes a neuromorphic analog CMOS controller for interlimb coordination in quadruped locomotion. Animal locomotion, such as walking, running, swimming, and flying, is based on periodic rhythmic movements. These rhythmic movements are driven by the biological neural network, called the central pattern generator (CPG). In recent years, many researchers have applied CPG to locomotion controllers in robotics. However, most of these have been developed with digital processors and, thus, have several problems, such as high power consumption. In order to overcome such problems, a CPG controller with analog CMOS circuit is proposed. Since the CMOS transistors in the circuit operate in their subthreshold region and under low supply voltage, the controller can reduce power consumption. Moreover, low-cost production and miniaturization of controllers are expected. We have shown through computer simulation, such circuit has the capability to generate several periodic rhythmic patterns and transitions between their patterns promptly.

A majority-logic device using an irreversible single-electron box

We present an analog neuron circuit consisting of a small number of metal-oxide semiconductor (MOS) devices operating in their subthreshold region. The dynamics of the circuit were designed to be equivalent to the well-known Volterra system to facilitate developing the circuit for a particular application. We show that a simple nonlinear transformation of system variables in the Volterra system enables designing a neuron-like oscillator, which can produce sequences in time of identically shaped pulses (spikes) by using current-mode subthreshold MOS circuits. We present experimental results of the fabricated neuron circuits as well as an application in an inhibitory neural network, where the neurons compete with each other in the frequency and time domains.

An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion

A floating-gate MOSFET device that can be used as a precision analog memory for neural network LSIs is described. This device has two floating gates. One is a charge-injection gate with a Fowler-Nordheim tunnel junction, and the other is a charge-storage gate that operates as a MOSFET floating gate. The gates are connected by high resistance, and the charge-injection gate is small so that its capacitance is much less than that of the charge-storage gate. By applying control pulses to the charge-injection gate, it is possible to charge and discharge the MOSFET floating gate in order to modify the MOSFET current with high resolution over 10 b. The charge injection can be carried out without disturbing the MOSFET output current with high voltage control pulses. This device is useful for on-chip learning in analog neural network LSIs. >

A subthreshold MOS neuron circuit based on the Volterra system

The device proposed here for future LSIs is based on a concept different from the Boolean equations usually used for representing digital functions. The unit function of this device is simple two-way switching and can be implemented utilizing various physical effects, such as optical switching, electron-wave modulation, and single-electron transport. Several possible device structures are presented, and a simulated result for a single-electron device is described. >

A floating-gate analog memory device for neural networks

A low-power CMOS current reference circuit was developed using a 0.35-μm standard CMOS process technology. The circuit consists of MOSFET circuits operating in the subthreshold region and uses no resistors. It compensates for the temperature effect on mobility μ and threshold voltage VTH of MOSFETs and generates a reference current that is insensitive to temperature and supply voltage. Theoretical analyses and experimental results showed that the circuit generates a stable reference current of 100 nA. The temperature coefficient of the current was 520 ppm/°C at best and 600 ppm/°C on average in the range of 0°C-80°C. The line regulation was 0.2%/V in a supply voltage range of 1.8-3 V. The power dissipation was 1 μW, and the chip area was 0.015 mm2. Our circuit would be suitable for use in subthreshold-operated power-aware large-scale integrations.

Binary-decision-diagram device

The inherent stochastic character of single-electron tunneling can be effectively utilized for creating novel electronic circuits having high-level functions. As a sample application, we present a stochastic-response circuit for implementing Boltzmann machine neurons. The circuit consists of a single-electron circuit operating under unstable conditions. It can produce an output of a random 1–0 bit stream with the probability for an output of 1 controlled by an input signal—a task that is difficult for conventional circuits using ordinary electronic devices.