Shin'ichiro Mutoh

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFETs in a single LSI. The low-threshold voltage MOSFETs enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFETs suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSIs. To demonstrate MTCMOSs effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application

A 1-V power supply low-power and high-speed 16-b fixed-point digital signal processor using a 0.5-/spl mu/m process has been developed for mobile phone applications. A 1-V multithreshold-voltage CMOS (MTCMOS) technology that uses both high-threshold-voltage and low-threshold-voltage transistors is one key to attaining low power consumption, keeping processing throughput high. A maximum operating frequency of 13.2 MHz and an energy consumption of 2.2 mW/MHz were achieved at 1 V. The second key to low-power operation is a power management scheme that uses a secondary embedded microprocessor. This proposed scheme minimizes the standby power in the waiting state by effectively controlling the sleep mode in the MTCMOS design. We confirmed that the standby leakage current was reduced three orders of magnitude and that the energy consumed in the waiting state was less than 1/10 of that consumed by conventional CMOS circuits with lowered supply voltage and threshold voltage but without power management.

A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application

A low-power digital signal processor (DSP) is the key component for battery-driven mobile phone equipment since a vast amount of data needs to be processed for multimedia use. Reduced supply voltage is a direct approach to power reduction. This 1 V DSPLSI with 26 MOPS and 1.1 mW/MOPS performance adopts a multi-threshold-voltage CMOS (MTCMOS) technique. A small embedded power-management processor decreases power during waiting periods.

A 1-V high-speed MTCMOS circuit scheme for power-down applications

A new MTCMOS concept is proposed for power-down applications. This concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied. Low-power, high-speed performance are achieved by separating the holding circuit from the critical path. A scan register has been developed based on this concept. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology.

Design method of MTCMOS power switch for low-voltage high-speed LSIs

The design of the power switch which turns on and off the power supply to the logic gates is essential to low-voltage high-speed circuit techniques such as multi-threshold voltage CMOS (MTCMOS). This is because this switch influences the speed, area, and power of a low-voltage LSI. This paper describes the influences of the power switch on the circuit performance in detail, and proposes a systematic method for designing a power switch which takes them into consideration for the first time. The main feature of this method, called the average-current method, is the use of the average current consumed in an LSI to determine the power-switch size. This makes it easy for designers to determine the minimum size of the power-switch needed to satisfy the required speed, which results in minimizing the area penalty and the standby power. Useful analytical formula and the practical determination flow are also described. Measurement of an actual 0.25 /spl mu/m MTCMOS/SIMOX 290-Kgate LSI operating at 1 V confirmed the effectiveness of this method. This method estimated well the required power-switch width, and as a result it reduced the area penalty and standby current by about 80% compared to the conventional design scheme.

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution

Four definitions of static random access memory (SRAM) cell write margins (WMs) were reexamined by analyzing the dependence of the WM on the SRAM cell transistor threshold voltages (Vths) in order to find a preferable definition. The WM is expected to obey the normal distribution if the differential coefficients of the WM to Vths are constant over a wide range of Vth variations. This means that the write yield can be easily predicted by a small number of measured samples. Using SPICE in 45-nm technology, we examined which definition had Vth linearity, as well as giving an accurate write limit. The distribution predicted from the linearity was verified by the Monte Carlo simulation. As a result, the definition proposed by Gierczynski was found to be the most suitable definition for predicting the distribution and the write yield.

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit

An adiabatic 64-kb SRAM circuit with shared reading and writing ports was designed, which enables gradual charging and discharging while maintaining a large VDD so that the problems of VT variation and electromigration in the nanocircuit can be solved. In the writing mode, the voltage of the memory cell ground line is increased to VDD/2 gradually, and the nMOSFET is turned off so that the memory cell ground line is set in a high-impedance state. Data can then be written easily by decreasing the voltage of one bit line adiabatically, while the voltage of the other bit line remains high. For reading, using the shared reading port, the voltage swing of the global bit-line can be decreased to VDD/4 so that the problems of electromigration can be solved. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and confirmed that the number of transistors in the cell is quasi-six. In addition, two types of new step voltage circuits with tank capacitors are proposed. One is for producing the memory cell ground line voltage and the other for charging the word line voltage adiabatically. Spontaneous step voltage formation is confirmed experimentally.

Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications

Nanowatt-power circuit techniques that could overcome the critical bottlenecks preventing the realization of dust-size battery-less sensor nodes are reported. Sensor networks deploying large numbers of nodes are anticipated for “ambient intelligence” [1]. For such networks, the sensor nodes should be miniaturized to the size of dust and be maintenance-free because battery-powered matchbox-sized nodes would be difficult to distribute in large numbers (100 to 1000, for instance) in rooms, and replacing the batteries would be very time-consuming. When the size of a power source is miniaturized to a few mm3, generated power is lowered to the nano-watt-level according to energy density limitations [2]. When the generated power is smaller than the power used for radio, sensor nodes have to accumulate energy [1]. The basic concept of a sensor node with functions for energy accumulation is shown in Fig. 27.10.1. The node contains the function blocks for power generation, power management, sensing, and radio. The power-management block accumulates energy to the accumulation capacitor, which is large enough for radio. When the voltage monitor detects that the voltage of the accumulated energy has reached the voltage needed for radio, the sensing block is activated. Then, the radio block transmits the sensed data when an event occurs. In this mode of operation, the voltage monitor for controlling the switch should operate with sub-nanowatt-level power dissipation because the monitor operates continuously during energy accumulation. Moreover, the power for sensing needs to be reduced to the sub-nanowatt level since the sensing function needs to be active after energy accumulation. On the other hand, the previous works for capacitive-sensing [3–4] and voltage reference [5] consume more than sub-microwatt since they use amplifiers and DC-biased resistors. To solve these problems, we use a voltage-monitoring circuit for power management and a vibration-sensing circuit that can operate even when the power source generates only nanoampere-level currents.

Power management technique for 1-V LSIs using embedded processor

A new power management technique is proposed for low-power, high-speed LSIs. This technique reduces the power consumption and enhances the performance of an LSI by using an embedded small processor to control the sleep modes and the processing of the LSI. Using this technique for a low-power DSP, the total power is reduced to about 10% of one without this technique, while maintaining the speed performance in 1-V LSIs.

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

The stability of a stepwise waveform of an adiabatic charge recycling circuit with tank capacitors is investigated. We propose a new tank capacitor circuit with two-string capacitor arrays. We experimentally confirmed the stability of the five-step waveform from the tank capacitors. The voltage changes of tank capacitors in the experiment are consistent with the simulation. The power consumption is reduced to one-fifth due to the five-step waveform. We analyze the stability using matrix theory. The results prove that the step waveform is stable for any circuit topology. Moreover, we consider the effects of conductors fixed at a certain voltage and floating conductors and confirm the system is stable using matrix theory.