Masayuki Yoshiki

Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier

We verified the effect of Ti layer insertion on stress induced void formation in wide Cu lines where voids were formed under via. In order to improve adhesion property between via and underlying Cu, PVD-Ti was inserted under Ta/TaN barrier. When nominal 30 nm thick PVD-Ti layer was inserted (Ti thickness at via bottom was about 8 nm), the failure was sufficiently suppressed without degrading the electromigration resistance. In addition, the via resistance was reduced by 25% compared with conventional Ta/TaN barrier structure, while the Cu metal resistivity was unchanged by the Ti insertion.

Fully large-scale integration-process-compatible Si field emitter technology with high controllability of emitter height and sharpness

We developed a fully large-scale integration (LSI)-process-compatible technology with excellent control of emitter shape for the first time. The fabricated emitter tip configuration has two-step-cone shape whose upper and lower cone configurations are controllable independently. While the upper parts determine the emitter tip sharpness and the apex angle, the lower parts determine the emitter height by utilizing two-step thermal oxidation for emitter tip sharpening in addition to anisotropic reactive ion etching for the emitter height control. The stable and uniform thermal oxidation for sharpening emitters produces excellent uniformity, and the process, without liftoff, is matched with Si LSI technology completely. The obtained 1944 tip emitter with 800 nm gate diameter showed low threshold voltage of 35 V.

Si field emitter array with 90-nm-diameter gate holes

We have successfully developed an extremely scaled-down Si field emitter array with 90-nm-diameter gates. The developed field emitter array has a unique two-step thick insulator underneath the gate electrode, which enables the insulator to be kept thick and which enables the long creeping distance between the emitter and the gate electrodes to be maintained even if the gate diameter is reduced. A fabricated field emitter array has an extremely small gate diameter of 90 nm and shows a low threshold voltage of 22 V at 1 nA/tip.

Novel field emitter array technology for subhalf-micron diameter gates

We have successfully developed a novel Field Emitter Array (FEA) technology with low-leakage current between each emitter and its sub-half-micron diameter gate. This FEA has 0.38 micron gates, its emission threshold voltage is 24 V, and its leakage current has been reduced to less than a tenth of previous levels.

A novel field emitter array technology for sub-half-micron diameter gates

We have successfully developed a novel Field Emitter Array (FEA) technology with low-leakage current between each emitter and its sub-half-micron diameter gate. This FEA has 0.38 micron gates, its emission threshold voltage is 24 V, and its leakage current has been reduced to less than a tenth of previous levels.

A fully-LSI-process-compatible Si field emitter technology with high controllability of emitter height and sharpness

We developed a fully-LSI-process-compatible technology with excellent control of emitter shape for the first time. The fabricated emitter tip configuration has two-step-cone shape whose upper and lower cone configurations are controllable independently. While the upper parts determine the emitter tip sharpness and the apex angle, the lower parts determine the emitter height by utilizing two-step thermal oxidation for emitter tip sharpening in addition to anisotropic RIE for the emitter height control. The stable and uniform thermal oxidation for sharpening emitters realizes excellent uniformity, and the process without lift-off process is matched with Si LSI technology completely. The obtained 1944-tip emitter with 800 nm gate diameter showed low threshold voltage of 35 V.