Massimo Poli

A novel pseudo random bit generator for cryptography applications

In this paper, a novel pseudo random bit generator is presented. It exhibits better inviolability properties, with respect to the traditional one, and it can be efficiently used in cryptography applications where high security is required. The proposed circuit is based on the classical linear feedback shift register (LFSR) with the feedback network dynamically modified. It has been evaluated with the most common randomness tests, giving excellent results. Moreover, the main statistical properties of the novel generator have been compared with those of a LFSR of equivalent length. The results have shown an equivalent performance of the circuits under comparison.

Evaluation of energy consumption in RC ladder circuits driven by a ramp input

In this paper, the energy consumption of RC ladder networks, which can represent chains of transmission gate or long wire interconnections, is modeled. Their energy dependence on the input rise time is analyzed by assuming a ramp input waveform. Since the analysis can be carried out in a straightforward manner only for very simple RC ladder networks, the exact analysis is first limited to asymptotic values of the input rise time T (i.e., for T/spl rarr/0 and T/spl rarr//spl infin/). Successively, the energy expression is extended to arbitrary values of the input rise time by introducing a suitable equivalent first-order RC circuit, whose resistance and capacitance are simply related to the resistances and capacitances of the original network. The energy expression found is useful for pencil-and-paper evaluation and affords an intuitive understanding of the network dissipation, since each term has an evident physical meaning. By comparison with SPICE simulations, the energy expression proposed is showed to be accurate enough for modeling purposes.

A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits

This paper discusses a general model of differential power analysis (DPA) attacks to static logic circuits. Focusing on symmetric-key cryptographic algorithms, the proposed analysis provides a deeper insight into the vulnerability of cryptographic circuits. The main parameters that are of interest in practical DPA attacks are derived under suitable approximations, and a new figure of merit to measure the DPA effectiveness is proposed. Worst case conditions under which a cryptographic circuit should be tested to evaluate its robustness against DPA attacks are identified and analyzed. Several interesting properties of DPA attacks are also derived from the proposed model, whose fundamental expressions are compared with the counterparts of correlation power analysis attacks. The model was validated by means of DPA attacks on an FPGA implementation of the advanced encryption standard algorithm. Experimental results show that the model has a good accuracy, as its error is always lower than 2%.

Propagation Delay of an RC -Chain With a Ramp Input

In this brief, two simple semi-analytical models which allow the estimation of the propagation delay of an RC-chain with a linear input are presented. The closed-form models can be used to evaluate the propagation delay of wires in modern VLSI and ULSI processes. The two approximations, a continuous function and a piecewise function, exhibit a maximum error lower than 15% at the end of the chain. The models have been validated extensively through circuit simulations. In particular, 1000 different RC-chains have been considered and simulated demonstrating the accuracy of the proposed models with respect to the most widely used Elmore delay metric

Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms

In this paper, a general model of multibit Differential Power Analysis (DPA) attacks to precharged buses is discussed, with emphasis on symmetric-key cryptographic algorithms. Analysis provides a deeper insight into the dependence of the DPA effectiveness (i.e., the vulnerability of cryptographic chips) on the parameters that define the attack, the algorithm, and the processor architecture in which the latter is implemented. To this aim, the main parameters that are of interest in practical DPA attacks are analytically derived under appropriate approximations, and a novel figure of merit to measure the DPA effectiveness of multibit attacks is proposed. This figure of merit allows for identifying conditions that maximize the effectiveness of DPA attacks, i.e., conditions under which a cryptographic chip should be tested to assess its robustness. Several interesting properties of DPA attacks are derived, and suggestions to design algorithms and circuits with higher robustness against DPA are given. The proposed model is validated in the case of DES and AES algorithms with both simulations on an MIPS32 architecture and measurements on an FPGA-based implementation of AES. The model accuracy is shown to be adequate, as the resulting error is always lower than 10 percent and typically of a few percentage points.

Energy consumption in RC tree circuits

In this paper, resistance-capacitance (RC) tree networks are modeled in terms of their energy consumption associated with an input transition. This work significantly extends the results that the same authors previously obtained in the specific case of ladder networks with only ramp signals. The proposed approach to model the energy consumption is based on a single-pole approximation, in which an equivalent time constant is analytically derived from an exact analysis for very slow and very fast input transitions. The model is then extended to arbitrary values of the input rise time by exploiting some intrinsic properties of RC tree networks. The approach is completely analytical and leads to closed-form results. Analytical results are explicitly derived for different inputs, such as the ramp and the exponential waveforms which are usually encountered in current VLSI circuits, as well as the saturated sine input. Due to its simplicity, the proposed energy expression is suitable for pencil-and-paper evaluation and allows for an intuitive understanding of the network dissipation. The energy expression proposed is shown to be accurate enough for modeling purposes through comparison with SPICE simulations.

A gate-level strategy to design Carry Select Adders

This paper addresses the gate-level design of Carry Select Adders aiming at minimizing its delay through a proper selection of the Full Adder groups sizes. It starts from a rigorous timing analysis of the Carry Select Adder, from which a preliminary procedure is formulated to build an incomplete nearly-optimum adder. Then, the required number of bits is reached by adding remaining bits into proper blocks minimizing the delay increase. The design strategy proposed also accounts for the dependence of multiplexer (MUX) delay on its fan-out, in contrast to the usual and unrealistic assumption of a constant MUX delay. The strategy proposed is applied in several design cases, whose results shows that the delay achieved is usually minimum, and only in a few cases delay it is lower than 2% of the optimum.

Power modeling of precharged address bus and application to multi-bit DPA attacks to DES algorithm

In this communication, a model of the precharged bus power consumption in digital VLSI circuits is developed. This model is used to analytically evaluate the result of a multi-bit Differential Power Attack (DPA) to the address bus of cryptographic ICs running the DES algorithm. This attack to the address bus is based on the observation of its power consumption, and is well known to be a major threat to the security of the confidential information stored or processed by SmartCards. The results allow to achieve a quantitative model of the DPA attack effectiveness, and is useful as a theoretical basis to understand the trade-offs involved in DPA attacks. This deeper understanding is useful to identify the cases where a SmartCard under attack is weaker with respect to DPA attacks, i.e. when the power consumption reveals the maximum amount of information. Cycle-accurate simulations on DES encryption algorithm running on a MIPS32® architecture are used to validate the model and the underlying assumptions.

Techniques to enhance the resistance of precharged busses to differential power analysis

In this communication, different techniques to improve the resistance to Differential Power Analysis (DPA) attacks of precharged busses are discussed. These statistical attacks rely on the observation of the power consumption, and are very effective in recovering confidential information that are stored or processed in SmartCards running cryptographic algorithms. Accordingly, a few techniques to improve the information security by reducing the effectiveness of DPA attacks are discussed. These techniques are statistically analyzed and compared in terms of DPA resistance, power and area overhead. Finally, these techniques are mixed to improve the robustness to DPA attacks. Cycle-accurate simulations on DES encryption algorithm running on a MIPS32® architecture are used to validate the discussed techniques.

Propagation delay model of a current driven RC chain for an optimized design

This work presents models which evaluate the propagation delay of an RC chain driven by a step input current generator. Starting from a rule of thumb model, involving network parameter values, three different approximations have been devised. The approximated models are quite simple and can be adopted in finding the number of stages after which repeaters can be introduced. In particular, one of the models can be used to optimize the propagation delay when inserting repeaters in a chain of transmission gates. Results from the new approach were compared with the traditional one with optimization by Spice simulation using a 0.35-/spl mu/m CMOS technology. The optimization based on the proposed model shows both a lower propagation delay and the need for a smaller number of repeaters compared with the traditional approach, hence, lower power consumption and silicon area.