Rosario Mita

Design guidelines for reversed nested Miller compensation in three-stage amplifiers

The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using nulling resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-/spl mu/m process are found to be in good agreement with the expected results.

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-mum technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications

1.5-V CMOS CCII+ with high current-driving capability

A novel CMOS low-voltage positive current conveyor of second generation is described in this paper. This solution allows almost rail-to-rail input and output operation and a high driving capability, thanks to the adoption of a class AB current output stage. A prototype was fabricated in a 0.35-/spl mu/m technology and experimentally tested. Using a 1.5-V supply, the circuit exhibited an input resistance of lower than 100 /spl Omega/ at the input terminal and a better than /spl plusmn/0.9 mA current drive capability, which was about 45 times the quiescent current in the output branch. Good frequency performance was also obtained.

Gated-Clock Design of Linear-Feedback Shift Registers

In this paper, we will present a method to reduce the power consumption of the popular linear feedback shift register. The proposed scheme is based on the gated clock design approach and it can offer a significant power reduction, depending on technological characteristics of the employed gates. Moreover, the analytical condition that must be satisfied to achieve a power reduction of the gated-clock circuit has been found. Theoretical analysis was validated through many transistor-level SPECTRE simulations in CADENCE environment by using the 0.35- mum digital standard cells technology supplied by AMS. Simulation results have shown a power reduction of about 10% with a mean error of about 3% with respect to theoretical derivations.

Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers

A methodology to design high-speed power-efficient MOS current-mode logic (MCML) static frequency dividers is proposed. Analytical criteria to exploit the speed potential of MCML gates are first introduced. Then, an analytical strategy is formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, thereby reducing the overall power consumption. The proposed design approach is general and independent of the process adopted. Due to its simplicity, it can be used in a pencil-and-paper approach, avoiding a tedious and time-consuming trial-and-error approach based on simulations. Moreover, the analytical approach allows for a deeper understanding of the power-delay tradeoff involved in the design. As a design example, a 1:8 frequency divider is designed and simulated by using a 0.18-mum CMOS process

Low-voltage high-drive CMOS current feedback op-amp

A novel CMOS current feedback op-amp is presented. The solution works using a low supply voltage and provides a wide input/output swing as well as a high current driving capability. Experimental results from a prototype implemented in a 0.35-/spl mu/m technology and powered with 1.5 V are also given. The circuit exhibits a better than 500 kHz closed-loop bandwidth and a /spl plusmn/1 mA current drive capability.

High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes

In this paper, an innovative active-quenching and recharging circuit for single-photon avalanche diodes is presented. The proposed driver is very fast and extremely compact. It is based on a novel quenching paradigm that heavily reduces dead time, which now is only limited by the sensor rather than the circuit itself. To test speed performance, we designed the circuit with a dielectrically insulated 2-mum technology supplied by ST Microelectronics and carried out postlayout simulations using SPECTRE. Moreover, the functionality of the circuit was also validated with experimental measurements on a medium scale integration (MSI) discrete implementation.

Behavioral modeling of statistical phenomena of single-photon avalanche diodes

In this paper, we present an accurate behavioral model for simulating single-photon avalanche diodes (SPADs). The device operation is described using the Verilog-A description language, which is an analog extension of the common digital hardware description language. The derived model is able to emulate the static, the dynamic behavior and the main statistical effects of an SPAD, such as the turn-off probability, the dark-count and the after-pulsing phenomena. Spectre simulations reveal the validity of the approach showing a good matching between the behavior of the proposed model and experimental results reported in the literature. Copyright

Accurate model for single-photon avalanche diodes

An accurate model useful for simulating single-photon avalanche diodes including biasing circuits is presented. The authors developed the model using Verilog-A codes to describe both static and dynamic behaviours. The derived model fits experimental results extracted from practical devices better than the one used in the open literature. SPECTRE simulations confirmed the validity of the proposed model, which avoids convergence problems and also shows a higher accuracy than traditional models.

A novel pseudo random bit generator for cryptography applications

In this paper, a novel pseudo random bit generator is presented. It exhibits better inviolability properties, with respect to the traditional one, and it can be efficiently used in cryptography applications where high security is required. The proposed circuit is based on the classical linear feedback shift register (LFSR) with the feedback network dynamically modified. It has been evaluated with the most common randomness tests, giving excellent results. Moreover, the main statistical properties of the novel generator have been compared with those of a LFSR of equivalent length. The results have shown an equivalent performance of the circuits under comparison.