G. Di Cataldo

New CMOS current mirrors with improved high‐frequency response

A new CMOS current mirror is presented which has the static characteristic of the cascode current mirror and a high-frequency performance equivalent to or better than that of the simple current mirror. Moreover, the circuit proposed does not present the instability problem of the improved cascode utilized to increase the high-frequency response. The circuit is designed using CMOS 2 μm technology with various aspect ratios and simulated with the SPICE programme.

Optimized design of high fan-in multiplexers using tri-state buffers

In this work, a strategy to design high-fan-in multiplexers with minimum delay is proposed. The work extends the optimization proposed by Lin (2000) to the case of switches with driving capability, that exhibit better performance in terms of noise immunity as well as being suitable for voltage scaling, which are becoming increasingly important properties in todays CMOS technologies. Moreover, the design strategy explicitly accounts for wiring parasitics in design equations. The criteria found are simple and useful right from the early design phases, as well as being independent of the technology used. In addition, an approximate expression of delay is given to predict the speed performance achievable for a given process before actually carrying out the optimized design. As a design example, a 256-input multiplexer was designed and simulated after extracting the parasitics from layout using a 0.35-/spl mu/m CMOS process. The predicted delay agrees well with simulation data.

Modeling of Feedback Analog Circuits with VHDL

In this communication we develop an accurate procedure to describe any feedback analog circuit through VHDL. We pay particular attention to the choice of the time parameter which makes possible the discretization of the continuous equations that regulate circuit behavior. An OpAmp buffer is modeled as an example circuit and simulation results are compared with those extracted by transistor level simulation performed by spectre. Model accuracy is evaluated for different values of the input signal and time parameter. Comparison goal is finding the dummy parameter value which gives the best trade-off between accuracy and speed improvement of the VHDL model with respect to the transistor level simulations.

An accurate offset-compensated current comparator

An offset-compensated current comparator is presented which provides an accuracy better than 30 nA. Moreover, the proposed topology allows a well-controlled input resistance and bias currents to be achieved. Simulated results from 2-/spl mu/m CMOS process are included.

Design guidelines for bipolar frequency dividers

In this paper, design of static current mode bipolar frequency dividers is addressed. Design criteria are provided to set bias currents of cascaded stages to achieve a high maximum operating frequency and keep power consumption as low as possible. In particular, bias current of the first stage is found according to speed requirements, while that of subsequent stages is progressively reduced at the minimum value that meets the speed constraint. The design equations are derived from timing analysis of frequency dividers by using simple delay models, and are simple enough to be used in a pencil-and-paper design. The design criteria are applied to the design of a 1/8 frequency divider in a bipolar process whose npn transistor has an f/sub T/ of 20 GHz. SPICE simulations agree well with theoretical results.

Double and triple charge pumps with mos diodes: Dynamic models to an optimized design

In this paper the dynamic models of the double and triple charge pumps are extended to circuits in which the diodes are realized with an MOS transistor having a drain-gate contact. In this circuit realization we must take into account the influence of the source-substrate voltage on the threshold voltage Vt. The effects of the source-substrate voltage on the dynamic behaviour are analysed and discussed in detail. Moreover, simple equations allowing one to perform a pencil-and-paper area-efficient optimized design are developed from the two new models. The models obtained are also validated by SPICE simulation of the circuit assuming a typical CMOS 3 μm process.

CMOS voltage feedback current amplifier

A CMOS current operational amplifier with constant closed-loop bandwidth properties and high linearity is described and analyzed. A low-voltage architecture is proposed and designed using a 0.3-Cm process. The circuit operates under a 2- V supply and dissipates 130 VW, while exhibiting a closed-loop bandwidth of about 2 MHz using a fixed 100-kOmega feedback resistor.

Gain-compensated sample-and-hold circuit for high frequency application

A novel and fast and accurate sample-and-hold circuit is presented which can be designed using conventional single stage amplifiers. The offset contribution to the output voltage is intrinsically compensated and the clock-feedthrough error can be reduced by slightly changing the clock phase scheme.

Current leakage and parasitic capacitance in transient second and triple order Cockcroft-Walton voltage multiplier

Theoretical models of the double and triple Cockroft-Walton voltage multiplier in the transient region are reported. The circuits discussed are commonly used in power ICs to allow the switching-on of an MOS device. The models take parasitic capacitance and current leakage into account.<<ETX>>

A generalization of Miller formulae for nonlinear feedback networks

The Miller theorem and its derivations are important tools to be used when analyzing feedback networks. However, they can be exploited in linear networks only. In this paper, we derive simple relationships which can be viewed as a generalization of the Miller theorem for nonlinear feedback elements. Their formulation results particularly useful when nonlinear circuits are analyzed to find, for example, harmonic distortion. Indeed, they allow to eliminate the nonlinear feedback, yielding more simple analytic relationships to be managed. The common emitter configuration is studied as an example, and comparisons between expected and simulated data confirm the validity and the accuracy of the analysis developed.