Matthew P. Crowley

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

A 512-Mb one-time-programmable memory is described, which uses a transistorless two-terminal memory cell containing an antifuse and a diode. Cells are fabricated in polycrystalline silicon, stacked vertically in eight layers above a 0.25-/spl mu/m CMOS substrate. One-time programming is performed by applying a high voltage across the cell terminals, which ruptures the antifuse and permanently encodes a logic 0. Unruptured antifuses encode a logic 1. Cells are arranged in 8-Mb tiles, 1 K rows by 1 K columns by 8 bits high. The die contains 72 such tiles: 64 tiles for data and eight tiles for error-correcting code bits. Wordline and bitline decoders, bias circuits, and sense amplifiers are built in the CMOS substrate directly beneath the memory tiles, improving die efficiency. The device supports a generic standard NAND flash interface and operates from a single 3.3-V supply.

512 Mb PROM with 8 layers of antifuse/diode cells

A 3.3 V, 512 Mb PROM uses a transistorless memory cell containing an antifuse and diode. A bit area of 1.4F/sup 2/ including all overhead is achieved by stacking cells 8 high above the 0.25 /spl mu/m CMOS substrate. Read bandwidth is 1 MB/s and write bandwidth is 0.5 MB/s. A 72 b Hamming code provides fault tolerance.

A seventh-generation x86 microprocessor

An out-of-order, three-way superscalar /spl times/86 microprocessor with a 15-stage pipeline, organized to allow 600 MHz operation, can fetch, decode, and retire up to three /spl times/86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously dispatch up to nine operations to seven integer and three floating-point execution resources. A sophisticated, cell-based design technique and judicious application of custom circuitry permit the development of a processor with an aggressive architecture and high clock frequency with a rapid design cycle. Design-for-test techniques such as scan and clock bypassing permit straightforward testing and debugging of the part.

An X86 microprocessor with multimedia extensions

This sixth-generation X86 instruction-set compatible microprocessor implements a set of multimedia extensions. Instruction predecoding to identify instruction boundaries begins during filling of the 32 kB two-way set associative instruction cache after which the predecode bits are stored in the 20 kB predecode cache. The processor decodes up to two X86 instructions per clock, most of which are decoded by hardware into one to four RISC-like operations, called RISC86 Ops, whereas the uncommon instructions are mapped into ROM-resident RISC sequences. The instruction scheduler buffers up to 24 RISC86 operations, using register renaming with a total of 48 registers. Up to six RISC86 instructions are issued out-of-order to seven parallel execution units, speculatively executed and retired in order. The branch algorithm uses two-level branch prediction based on an 8192-entry branch history table, a 16-entry branch target cache and a 16-entry return address stack. The 10.18/spl times/15.38 mm/sup 2/ die contains 8.8M transistors. The chip is in 0.35 /spl mu/m CMOS using five layers of metal, shallow trench isolation, and tungsten local interconnect.

A 7/sup th/-generation x86 microprocessor

The AMD-K7 (TM) processor is an out-of-order, three-way superscalar x86 microprocessor with a 15-stage pipeline, organized to allow 500+MHz operation. The processor can fetch, decode, and retire up to three x86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously issue up to nine operations to seven integer and three floating point execution resources. The cache subsystem and memory interface minimize effective memory latency and provide high bandwidth data transfers to and from these execution resources. The processor contains separate instruction and data caches, each 64 kB and two-way set-associative. The data cache is banked and supports concurrent access by two loads or stores, each up to 64 b in length. The processor contains logic to directly control an external L2 cache. The L2 data interface is 64 b wide and supports bit rates up to 2/3 the processor clock rate. The system interface consists of a separate 64 b data bus.