Bendik Kleveland

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

A 512-Mb one-time-programmable memory is described, which uses a transistorless two-terminal memory cell containing an antifuse and a diode. Cells are fabricated in polycrystalline silicon, stacked vertically in eight layers above a 0.25-/spl mu/m CMOS substrate. One-time programming is performed by applying a high voltage across the cell terminals, which ruptures the antifuse and permanently encodes a logic 0. Unruptured antifuses encode a logic 1. Cells are arranged in 8-Mb tiles, 1 K rows by 1 K columns by 8 bits high. The die contains 72 such tiles: 64 tiles for data and eight tiles for error-correcting code bits. Wordline and bitline decoders, bias circuits, and sense amplifiers are built in the CMOS substrate directly beneath the memory tiles, improving die efficiency. The device supports a generic standard NAND flash interface and operates from a single 3.3-V supply.

Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design

The increasing number of interconnect layers that are needed in a CMOS process to meet the routing and power requirements of large digital circuits also yield significant advantages for analog applications. The reverse thickness scaling of the top metal layer can be exploited in the design of low-loss transmission lines. Coplanar transmission lines in the top metal layers take advantage of a low metal resistance and a large separation from the heavily doped silicon substrate. They are therefore fully compatible with current and future CMOS process technologies. To investigate the feasibility of extending CMOS designs beyond 10 GHz, a wide range of coplanar transmission lines are characterized. The effect of the substrate resistivity on coplanar wave propagation is explained. After achieving a record loss of 0.3 dB/mm at 50 GHz, coplanar lines are used in the design of distributed amplifiers and oscillators. They are the first to achieve higher than 10 GHz operating frequencies in a conventional CMOS technology.

Monolithic CMOS distributed amplifier and oscillator

CMOS implementations for RF applications often employ technology modifications to reduce the silicon substrate loss at high frequencies. The most common techniques include the use of a high-resistivity substrate (/spl rho/>10 /spl Omega/-cm) or silicon-on-insulator (SOI) substrate and precise bondwire inductors. However, these techniques are incompatible with low-cost CMOS manufacture. This design demonstrates use of CMOS with a conventional low-resistivity epi-substrate and on-chip inductors for applications above 10 GHz.

512 Mb PROM with 8 layers of antifuse/diode cells

A 3.3 V, 512 Mb PROM uses a transistorless memory cell containing an antifuse and diode. A bit area of 1.4F/sup 2/ including all overhead is achieved by stacking cells 8 high above the 0.25 /spl mu/m CMOS substrate. Read bandwidth is 1 MB/s and write bandwidth is 0.5 MB/s. A 72 b Hamming code provides fault tolerance.

High-frequency characterization of on-chip digital interconnects

On-chip inductance is becoming increasingly important as technology continues to scale. This paper describes a way to characterize inductive effects in interconnects. It uses realistic test structures that study the effect of mutual couplings to local interconnects, to random lines connected to on-chip drivers, and to typical power and ground grids. The use of S parameters to characterize the inductance allows a large number of lines to be extracted while requiring only a small overhead measurement of dummy open pads to remove measurement parasitics. It also enables direct extraction of the frequency-dependent R, L, G, C parameters. The results are summarized with curve-fitted formulas of inductance and resistance over a wide range of line spacings and line widths. The significance of the frequency dependence is illustrated with transient analysis of a typical repeater circuit in a 0.25-/spl mu/m technology. A model that captures the frequency dependency of the extracted parameters accurately predicts the performance of a new inductance-sensitive ring oscillator.

Distributed ESD protection for high-speed integrated circuits

Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models. The large area of the distributed ESD scheme could limit its application to designs such as distributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss transmission lines in addition to a conventional ESD device.

50-GHz Interconnect Design in Standard Silicon Technology

Coplanar waveguides were fabricated in a process that emulates silicon CMOS technologies with 5 to 10 metal layers. The observed S21 loss of 0.3dB/mm at 50 GHz is among the lowest ever reported with standard Al interconnects on Si/SiO2. Optimum design parameters were counter-intuitive: in some frequency ranges, the lowest loss was achieved with relatively narrow lines over a low-resistivity substrate. This was exploited in the design of transmission lines that are fully compatible with a CMOS technology. The process emulation was calibrated with a commercial 4-layer Al/Cu CMOS technology.

On-chip inductance modeling of VLSI interconnects

At gigahertz frequencies, long interconnect wires exhibit transmission line behavior. Using copper and wider wires for major signal and power/ground lines, inductive impedance (j/spl omega/L) could become comparable to the resistive component of the wire (R). Due to the inductance, delay increases, over-shoot occurs, and inductive crosstalk can no longer be ignored. Inductive effects were recently demonstrated in 4 mm-long lines in a 0.25 /spl mu/m process. The extracted delays of a typical clock line from this test chip are shown. While the delay is a linear function of line length, the RC delay increases with the square of the line length. As a result, the inductive effects are actually more prominent for lines with intermediate lengths. The inductive effects for the intermediate length buses as well as local clocks must be considered. As technology is scaled, the gate delay time will continue to be reduced while the delay of short, low-resistive clock lines will remain constant. The inductive effects will therefore become prominent for progressively short lines. The article shows simulated inductance effects on crosstalk. Larger coupling and ringing effects are observed when inductive coupling is included in the simulation. Currently, the inductive effects are only considered for a few global clocks and buses, which is insufficient for future designs. Although 3D electromagnetic full wave solvers are available, they cannot manage the complexity of todays integrated circuits. To model the inductive effects of intermediate-length buses as well as local clocks, a fast automated inductance extraction and verification tool is necessary.

Line inductance extraction and modeling in a real chip with power grid

A realistic power grid and pseudo-random signal lines connected to on-chip drivers are included for accurate extraction of the parasitic inductance in a 5-metal layer 0.25-/spl mu/m CMOS technology. A new ring oscillator for the extraction of signal delay and characteristic impedance is demonstrated. The increase of signal delay due to mutual inductance of clock lines is measured directly with S-parameter characterization techniques.

On-chip interconnect inductance - friend or foe

Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, the extraction of wire inductance is not just dependent on the immediate neighboring environment. This paper discusses the various difficulties of extracting inductance of randomly placed wires in a typical chip environment. With dedicated return path, the wire inductance can be controlled and benefit the design of high-speed circuits. Specific examples are illustrated.