Matthew S. Doyle

Z-Axis NEXT & FEXT Reduction: Broadside Coupling Reduction Using Cu Vacuum Deposition in Mesh Reference Circuits

Signal integrity (SI) and cross-talk concerns play significant roles constraining design options for low-cost, high speed interconnect solutions. The electrical packaging and signal integrity engineers must focus on SI and noise concerns even though the cost pressure continues to drive for the use of lower cost packaging along with increased overall function. Target cost trends have caused designers to investigate chip-on-flex and other integrated flexible circuit interconnect solutions. A significant portion of all flexible circuit designs utilize mesh referencing planes to improve mechanical flexibility or achieve target characteristic impedances. These resulting geometries have the potential to create compromised transmission line topologies and negatively impact SI. This paper will introduce the design performance compromises involved with mesh reference plane constructs, their impact on Signal Integrity, the challenging simulation analysis, and product design. Specifically, this research will investigate the application of copper vacuum deposition as a potential method to address these performance trade-offs associated with typical mesh reference plane topologies .