Maxat Touzelbaev

Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates

Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

Thermal characterization of Bi2Te3/Sb2Te3 superlattices

Superlattices offer the potential to enhance the figure of merit for thermoelectric cooling by increasing the Seebeck coefficient while decreasing the thermal conductivity compared to bulk samples. The large bulk value of ZT makes superlattices containing Bi2Te3 attractive for demonstrating benefits of using low-dimensional materials in thermoelectric applications. The present work describes measurements of the effective thermal conductivity normal to Bi2Te3/Sb2Te3 superlattices deposited on GaAs using noncontact pulsed laser heating and thermoreflectance thermometry. The data show a strong reduction in the effective thermal conductivity of the Bi2Te3/Sb2Te3 superlattices compared to bulk Bi2Te3, which can further increase thermoelectric figure of merit. The dependence of thermal conductivity on superlattice period is found to be weak, particularly at periods above 60 A. This indicates that disorder in Bi2Te3/Sb2Te3 superlattices may limit the heat conduction process at shorter periods than in Si/Ge super...

Measurement of the thermal conductivity anisotropy in polyimide films

Polymer films are playing an important role in the development of micromachined sensors and actuators, fast logic circuits, and organic optoelectronic devices. The thermal properties of polyimide films govern the temporal response of many micromachined thermomechanical actuators, such as ciliary arrays. This work develops three experimental techniques for measuring both the in-plane and the out-of-plane thermal conductivities of spin-coated polyimide films with thicknesses between 0.5 and 2.5 /spl mu/m, which are common in MEMS. Two of the techniques use transient electrical heating and thermometry in micromachined structures to isolate the in-plane and out-of-plane components. These techniques establish confidence in a third, simpler technique, which measures both components independently and uses IC-compatible processing. The data illustrate the anisotropy in the thermal conductivity of the polyimide films investigated here, with the in-plane conductivity larger by a factor between four and eight depending on film thickness and temperature. The anisotropy diminishes the time constants of thermal actuators made from polyimide films.

Thermal conductivity measurements of thin-film resist

In electron-beam and photolithography, local heating can change the resist sensitivity and lead to variations in significant critical dimension. Existing models suffer from the lack of experimental data for the thermal properties of the polymer resist films. We present the measurements of both out-of-plane and in-plane thermal conductivity of thin resist films following different exposure conditions. An optical thermoreflectance technique was used to characterize out-of-plane thermal conductivity; the out-of-plane thermal conductivity of exposed SPR™-700 resist increases as a function of exposure dose. We also designed and fabricated a free-standing micro-electrode structure for measuring the in-plane thermal conductivity and results for poly(methylmethacrylate) films were obtained, indicating that, unlike polyimide films, there is no appreciable anisotropic behavior.

Impact of nucleation density on thermal resistance near diamond-substrate boundaries

Existing theory cannot account for the experimentally-observed thermal boundary resistance between deposited layers and substrates at room temperature. This is due to microstructural disorder in the deposited film within tens of nanometers of the interface. This work develops a model for the resulting thermal resistance near diamond-substrate interfaces, where the best deposition processes continue to yield high concentrations of amorphous inclusions and nanocrystalline material. The model relies on phonon transport theory and a novel subdivision of the near-interfacial region, which shows that the resistance is governed by the number of diamond nucleation sites per unit substrate area, i.e. The nucleation density. The predictions are consistent with experimental data for diamond-silicon interfaces and indicate that the resistance reaches a minimum for a nucleation density near 10{sup 10} cm{sup {minus}2}. This work facilitates the development microstructures that benefit more strongly from the excellent thermal-conduction properties of diamond.

Indium thermal interface material development for microprocessors

Optimal thermal design of high-power electronic components often requires use of solder-type thermal interface materials. Pure indium solder provides best combination of mechanical and thermo-mechanical properties for efficient thermal design. Two indium TIM assembly approaches were investigated: pre-attach approach and preform approach. Pre-attach refers to bonding indium to the lid cavity first, prior to microprocessor lid attach. Preform refers to direct bonding of indium to lid and silicon in a single reflow process. In the pre-attach approach, indium preform is attached to nickel-plated lid without gold metallization with aggressive flux. This type of flux must be cleaned thoroughly prior to microprocessor lid attach to avoid corrosion. After reflow, indium takes the shape of a dome in the lid cavity. This dome-shape indium can cause lid tilt reject during lid attach. Therefore, a follow-up coining step is required to flatten the indium dome prior to lid attach.

High-Efficiency Transient Temperature Calculations for Applications in Dynamic Thermal Management of Electronic Devices

The highly nonuniform transient power densities in modern semiconductor devices present difficult performance and reliability challenges for circuit components, multiple levels of interconnections and packaging, and adversely impact overall power efficiencies. Runtime temperature calculations would be beneficial to architectures with dynamic thermal management, which control hotspots by effectively optimizing regional power densities. Unfortunately, existing algorithms remain computationally prohibitive for integration within such systems. This work addresses these shortcomings by formulating an efficient method for fast calculations of temperature response in semiconductor devices under a time-dependent dissipation power. A device temperature is represented as output of an infinite-impulse response (IIR) multistage digital filter, processing a stream of sampled power data; this method effectively calculates temperatures by a fast numerical convolution of the sampled power with the modeled systems impulse response. Parameters such as a steady-state thermal resistance or its extension to a transient regime, a thermal transfer function, are typically used with the assumption of a linearity and time-invariance (LTI) to form a basis for device thermal characterization. These modeling tools and the time-discretized estimates of dissipated power make digital filtering a well-suited technique for a run-time temperature calculation. A recursive property of the proposed algorithm allows a highly efficient use of an available computational resource; also, the impact of all of the input power trace is retained when calculating a temperature trace. A network identification by deconvolution (NID) method is used to extract a time-constant spectrum of the device temperature response. We verify this network extraction procedure for a simple geometry with a closed-form solution. In the proposed technique, the amount of microprocessor clock cycles needed for each temperature evaluation remains fixed, which results in a linear relationship between the overall computation time and the number of temperature evaluations. This is in contrast to time-domain convolution, where the number of clock cycles needed for each evaluation increases as the time window expands. The linear dependence is similar to techniques based on FFT algorithms; in this work, however, use of z-transforms significantly decreases the amount of computations needed per temperature evaluation, in addition to much reduced memory requirements. Together, these two features result in vast improvements in computational throughput and allow implementations of sophisticated runtime dynamic thermal management algorithms for all high-power architectures and expand the application range to embedded platforms for use in a pervasive computing environment.

Impact of experimental timescale and geometry on thin-film thermal property measurements

Integrated circuits require effective removal of increasing heat fluxes from active regions. Thermal conduction strongly influences the performance of micromachined devices including thermal actuators, Peltier-effect coolers, and bolometers. The simulation of these devices requires thermal property data for the thin-film materials from which they are made. While there are many measurement techniques available, it is often difficult to identify the most appropriate for a device. This article reviews thin-film thermal characterization methods with an emphasis on identifying the properties extracted by the techniques. The characteristic timescale of heating and the geometry of the experimental structure govern the sensitivity of the data to the in-plane and out-of-plane conductivities, the volumetric heat capacity, and the interface resistances of the film. Measurement timescales and geometry also dictate the material volume probed most sensitively within the film. This article uses closed-form and numerical modeling to classify techniques according to the properties they measure. Examples of reliably extracted properties are provided for some experimental configurations. This article simplifies the process of choosing the best characterization technique for a given application in microdevice thermal design.

Transient Frequency-Domain Thermal Measurements With Applications to Electronic Packaging

Non-uniform power distribution, increased die-size, and multiple-chip modules present new challenges for the thermal management of modern integrated circuit (IC) packages. Thermal characterization techniques capable of resolving partial thermal resistances at the component level have received increased emphasis in development of advanced packaging technologies. This paper aims to develop a practical method for thermal characterization of IC packages using the frequency-domain measurement technique as a complementary technique to the widely used time-domain thermal transient measurement technique. This paper discusses practical implementation of the technique and demonstrates both thermal modeling and experimental results. Thermal impedances measured in frequency-domain yield the structure function, which describes the dynamic thermal response of the device based on thermal RC network analysis. Various applications of this technique in thermal characterization of the IC packages subjected to field conditions are also discussed.

Impact of temperature-dependent die warpage on TIM1 thermal resistance in field conditions

The evolution of microprocessor architectures has driven semiconductor manufacturers making transition from ceramic to organic package substrate technology in order to take full advantage of the silicon advances. However, large mismatch in coefficients of thermal expansion (CTE) between silicon die and organic substrate results in significant die/package warpage that adversely impact the packages thermomechanical performance during assembly processes and longterm reliability in use conditions. In contrast to the extensive studies in various mechanical failures, little research effort has been pursued in the investigation of impacts from die warpage on package thermal performance and TIM degradations, mainly due to the limitation of existing steady-state and transient thermal characterization techniques. This work explores the application of frequency-domain thermal impedance measurement technique in study of impact on thermal resistance at TIM1 level from temperature-dependent die warp behavior in field conditions. Hysteresis loop of thermal impedance at TIM1 level as a function of junction temperature is observed which indicates the TIM delamination due to its failure to accommodate the temperature-dependent die warpage. Evaluations of TIM candidates with different bond-line thicknesses (BLT), TIM curabilities, and die sizes suggest that optimizations of BLT are required in order to meet both mechanical and thermal performance requirements.