Maxim S. Gorbunov

Modeling of Radiation-Induced Leakage and Low Dose-Rate Effects in Thick Edge Isolation of Modern MOSFETs

A procedure of SPICE parameters extraction for radiation-induced equivalent lumped parasitic transistor is proposed. Comparison of radiation-induced leakage current in test MOSFETs between total dose irradiation experiments and simulation results exhibits excellent agreement. Mathematical description of combined enhanced low dose-rate sensitivity and tunnel annealing effects as applied to the MOSFET subthreshold leakage has been developed. It has been numerically found that the ELDRS effects are significantly suppressed by the simultaneous tunnel annealing in the edge isolation of MOSFETs.

Design of 65 nm CMOS SRAM for Space Applications: a Comparative Study

We study the design of different SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the localization of a strike. DICE cells demonstrate about 2-3 orders of magnitude lower than cross-sections for 6T-cells due to the 2-μm nodal spacing of sensitive pairs. Solid and intermittent guard rings has high effectiveness in SEL elimination.

SET tolerance of 65 nm CMOS majority voters: A comparative study

We study the design of different majority voters based on a commercial 65 nm CMOS technology, propose the test system and discuss the experimental results of heavy ion irradiation campaign and the proposed relative efficiency criterion for choosing the voter for a given TMR strategy.

Temperature Dependence of MCU Sensitivity in 65 nm CMOS SRAM

The temperature dependence of single-event upset multiplicity in 65 nm CMOS SRAM was investigated in this paper. Experimental results show significant increase of upset multiplicity over a temperature range of 300 to 400 K. Main physical mechanisms leading to the increase of the multiplicity of upsets at elevated temperatures were studied using three-dimensional (3-D) device simulations. A major role of upset voltage decrease and temperature dependence of the parasitic bipolar effect was established. Simulation results can be used for maximal upset multiplicity estimation.

Microdose Induced Drain Leakage Effects in Power Trench MOSFETs: Experiment and Modeling

We study experimentally and theoretically the micro-dose induced drain-source leakage current in the trench power MOSFETs under irradiation with high-LET heavy ions. We found experimentally that cumulative increase of leakage current occurs by means of stochastic spikes corresponding to a strike of single heavy ion into the MOSFET gate oxide. We simulate this effect with the proposed analytic model allowing to describe (including Monte Carlo methods) both the deterministic (cumulative dose) and stochastic (single event) aspects of the problem. Based on this model the survival probability assessment in space heavy ion environment with high LETs was proposed.

Fault-Tolerant SOI Microprocessor for Space Applications

The design and experimental results are presented for the fault-tolerant 0.35 ìm SOI CMOS microprocessor. DICE-like cells are shown to be vulnerable to SEU during “read” and “write” modes.

DICE-based muller C-elements for soft error tolerant asynchronous ICs

Muller C-element is one of the main parts of an asynchronous circuit. Being sequential by its nature, it is vulnerable to single event upsets (SEU). We propose three 65 nm CMOS circuit implementations of SEU tolerant C-element, whose tolerance is achieved by using of well-known DICE principle and is proved by SPICE simulations and semi-empirical estimations.

The scientific data acquisition system of the GAMMA-400 space project

The description of scientific data acquisition system (SDAS) designed by SRISA for the GAMMA-400 space project is presented. We consider the problem of different level electronics unification: the set of reliable fault-tolerant integrated circuits fabricated on Silicon-on-Insulator 0.25 mkm CMOS technology and the high-speed interfaces and reliable modules used in the space instruments. The characteristics of reliable fault-tolerant very large scale integration (VLSI) technology designed by SRISA for the developing of computation systems for space applications are considered. The scalable net structure of SDAS based on Serial RapidIO interface including real-time operating system BAGET is described too.

Semi-Empirical Method for Estimation of Single-Event Upset Cross-Section for SRAM DICE Cells

We propose a new semi-empirical method for estimation of Single Event Upset (SEU) cross-section for SRAM Dual Interlocked Cells (DICE) with known distance between neighboring sensitive volumes. The method is based on experimental analysis of SEU maps in sub-100 nm 6T SRAM along with layout considerations and SPICE simulations. It could help to significantly improve SEE robustness of modern CMOS VLSI by design.

Verilog-A Modeling of Radiation-Induced Mismatch Enhancement

Physical model of TID effects is embedded into BSIM3v3 model implemented using Verilog-A. Radiation-induced mismatch enhancement due to the combined action of technology variations and electrical bias difference is demonstrated by simulation. It is shown that the total ionizing dose degradation of circuit components under inequivalent electric field conditions could lead to mismatch of internal circuit parameters, which results in a change to circuit output mismatch parameters.