Anna B. Boruzdina

Design of 65 nm CMOS SRAM for Space Applications: a Comparative Study

We study the design of different SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the localization of a strike. DICE cells demonstrate about 2-3 orders of magnitude lower than cross-sections for 6T-cells due to the 2-μm nodal spacing of sensitive pairs. Solid and intermittent guard rings has high effectiveness in SEL elimination.

Automatic control system for memory chips performance in a radiation experiment

The paper analyzes the effectiveness of test algorithms of different duration during the functional control of static random access memory (SRAM) during the exposure to total ionizin dose (TID). The results of experimental research SRAM chips using an automated system based on the equipment PXI company National Instruments, justifying the use of the test algorithms such as “MARCH” (long-10N).

Effect of topological placement of memory cells in memory chips on multiplicity of cell upsets from heavy charged particles

An analysis of factors influencing operational reliability of memory chips has been performed. Different topological configurations of 6-transistors memory cells have been considered. Two configurations of cells most sensitive to the influence of multiple cell upsets (MCUs) have been identified.

Radiation-induced degradation in the dynamic parameters of memory chips

A technique for investigating CMOS memory chips under exposure to ionizing radiation and the results of their radiation tests are presented. Possible mechanisms of degradation and approaches to increasing the radiation resistance of integrated circuits by the access time criterion are analyzed. The effect of the nonuniform degradation of the access time depending on the address has been discovered and investigated in the experiment.

Temperature Dependence of MCU Sensitivity in 65 nm CMOS SRAM

The temperature dependence of single-event upset multiplicity in 65 nm CMOS SRAM was investigated in this paper. Experimental results show significant increase of upset multiplicity over a temperature range of 300 to 400 K. Main physical mechanisms leading to the increase of the multiplicity of upsets at elevated temperatures were studied using three-dimensional (3-D) device simulations. A major role of upset voltage decrease and temperature dependence of the parasitic bipolar effect was established. Simulation results can be used for maximal upset multiplicity estimation.

Verification of SRAM MСUs calculation technique for experiment time optimization

Single Event Upsets are a growing problem in memories. Therefore, it is important to properly characterize them in order to have a clear idea of how they behave in different applications and environments. Experiments using radiation are a usual method to achieve this goal. However, events produced in memories in this way tend to accumulate over time, being difficult to determine the true number of events that have affected the system. In this paper, several experiments have been conducted to validate a technique that allows calculating the number of real events that have been produced after a radiation test.

A method for registration of multiple cell upsets in high capacity memory cells induced by single nuclear particles

This study is devoted to the development of a method for the registration of multiple-cell upsets (MCUs) in memory cells induced by single nuclear particles. The presented results illustrate the possibility of finding MCUs in high capacity (higher than 1 Mbit) memory cells using the improved method.

Semi-Empirical Method for Estimation of Single-Event Upset Cross-Section for SRAM DICE Cells

We propose a new semi-empirical method for estimation of Single Event Upset (SEU) cross-section for SRAM Dual Interlocked Cells (DICE) with known distance between neighboring sensitive volumes. The method is based on experimental analysis of SEU maps in sub-100 nm 6T SRAM along with layout considerations and SPICE simulations. It could help to significantly improve SEE robustness of modern CMOS VLSI by design.

Method of SEU-Hardness Assurance for SRAM with Error Correction Using Focused Laser Sources

In this work the analysis of possible approaches to SEU-hardness testing for SRAM with error correction were conducted. Efficiency of the aproach proposed by Aeroflex was evaluated, and the results of experimental investigation for 16 Mbit SRAM under heavy ion and focused laser irradaition were provided.

Measurement system for test memory cells based on keysight B1500A semiconductor device analyzer running LabVIEW software

The Keysight B1500A semiconductor device analyzer based measurement system for test memory cells research is introduced. The connection of a device under test is described as well as the full list of the utilized equipment. The features of the Keysight equipment remote control by means of Keysight VISA are demonstrated; code examples in LabVIEW environment are also presented.