Md. Sajjad Rahaman

Crosstalk avoidance and error-correction coding for coupled RLC interconnects

On-chip interconnect delay and crosstalk noise have become an important factor for performance and signal integrity as a result of increase in device densities and operating clock frequency in deep sub-micrometer (DSM) VLSI circuits. With faster rise times and lower resistance, interconnects exhibit significant inductive effect compared to capacitive effect. Therefore, various existing coding techniques for capacitive crosstalk reduction in resistive-capacitance (RC) interconnects are not suitable for resistive-inductance-capacitance (RLC) interconnects in high-speed circuits. At the same time, on-chip interconnects are susceptible to various DSM noise sources. Error-correction coding (ECC) improves interconnect-reliability against DSM noise. This paper proposes a modified boundary shift coding technique that simultaneously addresses inductance-dominant cross-talk noise reduction and error-correction for coupled RLC interconnects. Results show that proposed coding achieves up to 50% reduction in additional wiring requirement.

Time diversity approach for intra-chip RF/wireless interconnect systems

Increasing operating frequency of current and future VLSI systems is putting physical constraint on hard-wired metal interconnect. RF/wireless interconnect is considered to be one of the alternatives to conventional metal interconnect. This paper evaluates the bit-error-rate (BER) performance of to coherent binary phase-shift keying (BPSK) with linear and systematic channel coding in an intra-chip RF/wireless interconnect system. The results indicate that for a certain range of received signal- to-noise (SNR) ratio, channel coding improves the performance of the RF/wireless interconnect system. It is also shown analytically that performance can be improved at low SNR with the application of time-diversity approach by using interleaver and deinterterleaver.

Bit-error-rate performance of inter-chip RF/wireless interconnect systems

With the ever increasing degrees of integration, and operating speed in ultra large-scale integrated (ULSI) circuits conventional approaches of hard-wired metal interconnects are encountering fundamental limits. Several revolutionary approaches have been proposed for an alternative to metal interconnect. One of the most feasible approaches is RF/wireless interconnects. This paper evaluates the system bit-error-rate (BER) performance in an inter-chip RF/wireless interconnect system. The results indicate that for a certain range of received signal-to-noise (SNR) ratio, error control coding (ECC) improves the performance of the RF/wireless interconnect system. It is also shown analytically that performance can be improved at low SNR with the application of time-diversity approach by using interleaver and deinterterleaver.

Improved ber performance in intra-chip rf/wireless interconnect systems

Increasing operating frequency of current and future VLSI systems is putting physical constraint on hard-wired metal interconnect. Several revolutionary approaches to interconnect have been proposed. One of the most feasible approaches is RF/wireless interconnects. This paper evaluates the bit-error-rate (BER) performance of a coherent binary phase-shift keying (BPSK) with linear and systematic channel coding in an intra-chip RF/wireless interconnect system. The results indicate that for a certain range of received signal-to-noise (SNR) ratio, channel coding improves the performance of the RF/wireless interconnect system. Digital implementation of the encoder and decoder circuit block is also shown.

Throughput and PN codephase acquisition for packet CDMA without preamble

In CDMA packet transmission, it is customary to start each packet with a preamble consisting of pseudo-random (PN) code with no data modulation. The preamble facilitates receiver acquisition of the spreading code alignment and this is essential for decoding the spread spectrum signal. Since packets are short, matched filters are employed to provide rapid acquisition and, in this case, we use a segmented matched filter that can provide codephase alignment even when there is data modulation. We thus eliminate the need for a packet preamble and improve the system throughput. However, if the matched filter fails to provide the correct codephase, a packet is lost. The probability of correct codephase detection (Pd) is increased by accumulating matched filter samples over several code cycles prior to making a decision. Using accumulated code cycles as a parameter, we present the probability of correctly detecting packet codephase as a function of the number of active co- users. Correct detection probabilities exceeding 99% are indicated from simulations with 25 co-users and 10 kHz Doppler shift or carrier frequency offset by accumulating five or more PN code cycles, using maximum selection detection criterion. Analysis and simulation also show that cyclic accumulation can improve packet throughput by 50% and by as much as 100% under conditions of high offered traffic and carrier frequency offset for both fixed capacity and infinite capacity packet systems.

Exploiting negative quantum capacitance of carbon nanotube FETs for low power applications

As conventional silicon-based CMOS technology is approaching its fundamental physical limits due to aggressive scaling, carbon nanotubes (CNTs) have been explored as promising candidates for both on-chip switching device and interconnect in post-Si nanoelectronics due to their superior current carrying and heat transfer capabilities. This paper investigates the prospect of bulk-modulated CNT field-effect transistors (CNTFETs) for low-power high-speed applications. It has been seen from atomistic density-functional theory (DFT) calculations that a negative quantum capacitance regime is achieved due to the one-dimensional (1D) screening of gate field in nanoscale CNTFETs. This unconventional negative quantum capacitance can be exploited to obtain a step-up voltage transformation at the gate of CNTFETs and, subsequently, sub-60mv/decade subthreshold swing. It is shown that a boosting efficiency greater than 2.2 is obtained at the gate of the CNTFETs.

Spatial- and temporal-reliability aware design for nano-scale VLSI circuits

This paper analyzes two of the most significant circuit reliability degradation phenomena in current CMOS technology, namely, temporal Negative Bias Temperature Instability (NBTI) for PMOS transistors and spatial Random Dopant Fluctuation (RDF) for both NMOS and PMOS nano-scale transistors. Among many models, Reaction-Diffusion model used for analyzing NBTI and width dependant model proposed for RDF simulations can currently get closest results to real cases. However, in most of the previous work, the causes and effects of NBTI and RDF were investigated individually. In this paper, we try to exploit how they act together to influence threshold voltage (Vth) and, hence, circuit performance. The simulation result shows that if a PMOS transistor suffers from severe RDF effect, NBTI effect inflicts more damage to it in terms of device performance. At the end, some possible methods of weakening the negative effects of NBTI and RDF are proposed and evaluated.

Addressing crosstalk issue in on-chip carbon nanotube interconnects using negative capacitance

Increasing Crosstalk is one of the most critical concerns for on-chip signal communication in nanoscale integrated circuits. This paper presents a method to use the negative capacitance technique to minimize crosstalk effects in carbon nanotube based interconnect, which is a potential future on-chip communication medium. With some assumptions, it is demonstrated that with careful synthesis and arrangement of CNT bundles, the capacitive coupling can be suppressed significantly. The focus of this paper is proving the concept, and the analysis is from mathematical and qualitative perspective. Its practicality depends on the success in synthesis and manufacturing of CNT in actual IC environment. In the context of current interests and progresses in CNT research it can be inferred the implementation challenge can be overcome in future.

Interconnect technique for sub-threshold circuits using negative capacitance effect

Global interconnects in deep-submicron (DSM) regime contribute a significant amount of power consumption and large propagation delay. As the global interconnect delay dictating the overall system performance, its variation also has larger impact on system performance in sub-threshold circuits. Due to the exponential relationship between weak-inversion current and the process-voltage-temperature (PVT) parameters, performance and power dissipation of sub-threshold circuits are exceedingly sensitive to PVT fluctuations. In order to build efficient sub-threshold circuits with higher operating frequencies, it is crucial to minimize the global interconnect delay and its variation. Shifting the interconnect driver transistors from the sub-threshold region to the super-threshold region is a way to secure a high-speed variation-tolerant interconnect system for sub-threshold circuits. Standard MOSFET with a ferroelectric insulator exhibits negative capacitance effect at low voltage and provides a lower than 60mV/dec swing. Therefore, it is more suitable for sub-threshold operation than bulk CMOS, and it can boost the applied gate voltage internally and results show a boosting efficiency of 100% could be obtained at a supply voltage of 0.2 volts. Besides, impact of process variation on sub-threshold operation with MOSFET with a ferroelectric insulator is also mentioned.

BER performance comparison between CDMA and UWB for RF/wireless interconnect application

In ultra large-scale integrated (ULSI) circuits conventional approaches of hard-wired metal interconnects are encountering fundamental limits. In order to get beyond this problem different revolutionary interconnect approaches have been explored. One of the most feasible approaches is RF/wireless interconnects, which are based on low-loss and dispersion-free microwave signal transmissions, near-field capacitive coupling and modern multiple-access technologies like code division multiple access (CDMA), frequency domain multiple access (FDMA), time domain multiple access (TDMA), ultrawideband (UWB) etc. In this paper BER performance of multi-carrier CDMA (MC-CDMA) and UWB transceiver for RF/wireless interconnect system are compared. Besides, required electronic overhead for these two transceivers is also mentioned.