Mehdi Hatamian

A real-time two-dimensional moment generating algorithm and its single chip implementation

We present a fast algorithm and its single chip VLSI implementation for generating moments of two-dimensional (2-D) digital images for real-time image processing applications. Using this algorithm, the number of multiplications for computing 16 moments of a 512 × 512 image is reduced by more than 5 orders of magnitude compared to the direct implementation; the number of additions is reduced by a factor of 4. This also makes the software implementation extremely fast. Using the chip, 16 moments μp,q(p = 0, 1, 2, 3, q = 0, 1, 2, 3) of a 512 × 512 8 bits/pixel image can be calculated in real time (i.e., 30 frames per second). Each moment value is computed as a 64- bit integer. The basic building block of the algorithm is a single-pole digital filter implemented with a simple accumulator. These filters are cascaded together in both horizontal and vertical directions in a highly regular structure which makes it very suitable for VLSI implementation. The chip has been implemented in 2.5 μ CMOS technology, it occupies 6100 μm × 6100 μm of silicon area. The chip can also be used as a general cell in a systolic architecture for implementing 2-D transforms having polynomial basis functions.

Design Considerations for a Real-Time Ocular Counterroll Instrument

A video-based technique for measuring the torsional movement of the eye (counterroll) by processing video images of the eyeball is presented. Spectral estimates show that most of the variance of the iris image is in the angular direction. It will be demonstrated that cross correlation between sequences that are obtained by circular sampling of the digitized image of the iris is sufficient to extract the counterroll information. Computation time for angular correlation is thus significantly reduced and real-time hardware implementation becomes feasible. As the result of a preprocessing step, we obtain the information about the horizontal and vertical movement of the eye and also the diameter of the pupil. To improve the measurement resolution, a fast second degree local least square interpolation of the cross-correlation function is used. Possible sources of error and the limitations of the algorithm will be studied. The results of the computer simulations made using the algorithm serve to experimentally confirm the error estimates. Application of the algorithm to photographically obtained image data from human subjects demonstrates its practicality on normal eyes. The system design for a device for measuring 3D movement of the eye will be discussed.

A 100 MHz 40-tap programmable FIR filter chip

The design and implementation of a single-chip programmable 40-tap finite impulse response (FIR) filter in 0.9 mu CMOS technology is described. The chip is fabricated and tested at sample rates up to 100 MHz. It performs over four billion multiply-add operations (12*10 bit multiplications and 26-bit additions) per second in less than 22 mm/sup 2/ of silicon area while dissipating about 3.1 W of power.<<ETX>>

Understanding Clock Skew in Synchronous Systems

Clock distribution and synchronization in synchronous systems are important issues especially as the size of the system and/or the clock rate increase. Minimization of clock skew has always been a major concern for the designers. Many factors contribute to clock synchronization and skew in a synchronous system. Among the major factors are: the clock distribution network, choice of clocking scheme, the underlying technology, the size of the system and level of integration, the type of material used in distributing the clock, clock buffers, and the clock rate. To be able to get around the problems related to clock skew and synchronization, one has to understand the effect that clock skew can have on the operation of a given system. In this paper we derive simple and practical formulations of these effects in terms of a few time-parameters that can be considered as properties of the individual modules and the clock network in a synchronous system. Knowing these time-parameters, one can determine the maximum throughput of a given system as well as its reaction to a change in clock skew. Three different clocking schemes, namely, edge-triggered, single-phase level sensitive, and two-phase clocking are considered. However, using the approaches discussed in this paper, the effect of clock skew for any other clocking scheme can be analyzed and formulated.

A 200 MHz CMOS broad-band switching chip

The architecture of a 32-channel, 200 MHz Batcher-Banyan fabric chip for broadband ATM packet switching is described, as well as the design methods required to develop a 380 K-transistor CMOS device that operates at these speeds under worst-case conditions. This device routes packets from 32 sources to any 32 destinations, is completely reconfigured each packet period, maintains priorities, supports contention resolution, and is a building block for larger switches. >

A fast pipelined CMOS SRAM

A fast synchronous pipelined CMOS static random access memory (SRAM) capable of reading and writing a new address every 10 ns is described. The design incorporates several interesting techniques-in particular, a novel sense amplifier based on a critically balanced cross-coupled inverter, and associated self-timed read/write logic. A 64-kbit block has been fabricated in the 0.9- mu m digital CMOS process, and tested with a cycle time of better than 10 ns. A 256-kbit version is being designed.<<ETX>>

The ATM physical layer

In this article, we present an overview of the physical layer specification of the emerging Asynchronous Transfer Mode (ATM) networks. These specifications concern the complete details of how to ship 53-byte ATM cells from Point A to Point B over a physical medium on a Local Area Network (WAN). While the task of defining the interfaces and line coding of the transceivers over different physical media is ongoing, the primary underlying theme has been the leveraging of existing standards and practices to the maximum extent possible.

The impact of high-T/sub c/ superconductivity on system communications

Reviews simple models for understanding the intrinsic behavior of superconducting striplines for frequencies much less than the gap frequency omega /sub g/, and low reduced temperatures. The effects of extrinsic factors such as nonideal stripline geometries and dielectrics are also examined. It is concluded that although based upon classical theory, these models are useful in providing performance estimates so that preliminary observations can be made regarding the application of high-T/sub c/ superconducting lines within digital computer systems. Finally, possible applications as well as performance questions regarding the use of high-T/sub c/ superconductors within contemporary and future digital systems are discussed. >

A 65 MHz 16-tap FIR filter chip with on-chip video delay lines

The VLSI design of a 16-tap finite impulse response (FIR) filter chip with programmable line delays for video applications is described. The chip is fabricated in 0.9- mu m CMOS technology. It is tested at sample rates up to 65 MHz. The chip contains about 600000 devices in less than 22 mm/sup 2/ of silicon area.<<ETX>>

A design environment for high performance VLSI signal processing

An environment for the full-custom design of high-sample-rate digital signal processing (DSP) VLSI circuits is described. An overall design methodology that allows for tradeoffs between algorithms, architecture, and layout is presented. Key CAD tools used in this methodology include architecture mapping, generators, symbolic layout, clock network analysis, and timing simulation. These tools allow designers to move rapidly from specification to layout while keeping a close check on performance parameters such as speed and power dissipation. Two high-speed video chips that were designed using these techniques are described.<<ETX>>