Sailesh K. Rao

The rectilinear steiner arborescence problem

The Rectilinear Steiner Arborescence (RSA) problem is “Given a setN ofn nodes lying in the first quadrant of E2, find the shortest directed tree rooted at the origin, containing all nodes inN, and composed solely of horizontal and vertical arcs oriented only from left to right or from bottom to top.” In this paper we investigate many fundamental properties of the RSA problem, propose anO(n logn)-time heuristic algorithm giving an RSA whose length has an upper bound of twice that of the minimum length RSA, and show that a polynomial-time algorithm that was earlier reported in the literature for this problem is incorrect.

A 100 MHz 40-tap programmable FIR filter chip

The design and implementation of a single-chip programmable 40-tap finite impulse response (FIR) filter in 0.9 mu CMOS technology is described. The chip is fabricated and tested at sample rates up to 100 MHz. It performs over four billion multiply-add operations (12*10 bit multiplications and 26-bit additions) per second in less than 22 mm/sup 2/ of silicon area while dissipating about 3.1 W of power.<<ETX>>

A 200 MHz CMOS broad-band switching chip

The architecture of a 32-channel, 200 MHz Batcher-Banyan fabric chip for broadband ATM packet switching is described, as well as the design methods required to develop a 380 K-transistor CMOS device that operates at these speeds under worst-case conditions. This device routes packets from 32 sources to any 32 destinations, is completely reconfigured each packet period, maintains priorities, supports contention resolution, and is a building block for larger switches. >

A fast pipelined CMOS SRAM

A fast synchronous pipelined CMOS static random access memory (SRAM) capable of reading and writing a new address every 10 ns is described. The design incorporates several interesting techniques-in particular, a novel sense amplifier based on a critically balanced cross-coupled inverter, and associated self-timed read/write logic. A 64-kbit block has been fabricated in the 0.9- mu m digital CMOS process, and tested with a cycle time of better than 10 ns. A 256-kbit version is being designed.<<ETX>>

The ATM physical layer

In this article, we present an overview of the physical layer specification of the emerging Asynchronous Transfer Mode (ATM) networks. These specifications concern the complete details of how to ship 53-byte ATM cells from Point A to Point B over a physical medium on a Local Area Network (WAN). While the task of defining the interfaces and line coding of the transceivers over different physical media is ongoing, the primary underlying theme has been the leveraging of existing standards and practices to the maximum extent possible.

A 65 MHz 16-tap FIR filter chip with on-chip video delay lines

The VLSI design of a 16-tap finite impulse response (FIR) filter chip with programmable line delays for video applications is described. The chip is fabricated in 0.9- mu m CMOS technology. It is tested at sample rates up to 65 MHz. The chip contains about 600000 devices in less than 22 mm/sup 2/ of silicon area.<<ETX>>

A design environment for high performance VLSI signal processing

An environment for the full-custom design of high-sample-rate digital signal processing (DSP) VLSI circuits is described. An overall design methodology that allows for tradeoffs between algorithms, architecture, and layout is presented. Key CAD tools used in this methodology include architecture mapping, generators, symbolic layout, clock network analysis, and timing simulation. These tools allow designers to move rapidly from specification to layout while keeping a close check on performance parameters such as speed and power dissipation. Two high-speed video chips that were designed using these techniques are described.<<ETX>>

Communication reduction for distributed sparse matrix factorization on a processor mesh

The problem of reducing the amount of interprocessor communication during the distributed factorization of a sparse matrix on a mesh-connected processor network is investigated. Two strategies are evaluated - 1) use of a fragmented distribution of row/columns of the matrix to limit the number of processors to which each row/column segment is transmitted, and 2) use of the elimination tree to permute the matrix so as to internalize as much of the communication as possible. Empirical evaluation of the schemes using matrices derived from circuit simulation shows significant reduction in the amount of communication for a 64 processor mesh.

The matrix transform chip

The matrix transform chip (MTC) is designed to perform matrix computations of the form Y=UDV where D is the input data matrix of 16-bit twos complement fixed-point numbers and U, V, are arbitrary coefficient matrices of the same precision. The data matrix D is input to the chip in raster scanned order at a maximum sample rate of 40 MHz, and the output matrix is provided in the same order. On a single chip, the maximum dimension of all matrices must be less than eight, but multiple chips can be cascaded to obtain arbitrary dimensions. The MTC consists of 16 16-bit parallel multipliers/40-bit accumulators, a kilobyte of dual-ported transposition static RAM, and a kilobyte of coefficient static RAM, arranged to interact in a regular iterative architecture. At peak operation, the MTC is capable of performing 0.64 billion fixed-point multiples, 0.64 billion 40-bit accumulates, along with 1.92 billion pseudorandom memory-access operations per second.<<ETX>>