Mehdi Si Moussa

Zero-temperature-coefficient biasing point of 2.4-GHz LNA in PD SOI CMOS technology

This paper reviews and analyzes a fully integrated low-noise amplifier (LNA) for low-power and high temperature applications, in 130 nm partially depleted silicon-on-insulator (SOI) CMOS technology. The LNA has been characterized over a temperature range from 25 to 200degC and designed using a cascode inductive source degeneration topology. Thanks to the SOI technology and the choice of the zero-temperature-coefficient (ZTC) bias point, the LNA measurements show a minor degradation of the gain due to the temperature variation for a power consumption of 2.3 mW under 1.2 V supply is applied. The effects of high temperature are observed on the gain of the LNA and on the SOI transistors in order to analyze the behavior of the LNA versus temperature effect.

High Temperature Antenna Switches in 130 nm SOI Technology

This paper presents the design and the behavior vs. temperature of RF antenna switches in a 130 nm SOI technology. The design is implemented using two types of transistors; floating body and body tied transistors. It is shown that the floating body transistor is the best candidate for the design of RF antenna switches implemented in a fully integrated RF communication system. Outstanding high temperature behavior is also emphasized on a temperature range from 25degC to

Behavior of a common source traveling wave amplifier versus temperature in SOI technology

In this paper, the design and the results of a CMOS Silicon-On-Insulator (SOI) traveling wave amplifier (TWA) versus temperature are presented. The four stage TWA is designed with a single common source n-MOSFET in each stage using a 130 nm SOI CMOS technology requiring a chip area of 0.75 mm/sup 2/. A gain of 4.5 dB and a unity-gain bandwidth of 30 GHz are measured at 1.4 V supply voltage with a measured power consumption of 66 mW. The designed circuit has been characterized over a temperature range from 25 to 300/spl deg/C. The performance degradation on the gain of the TWA, the SOI transistors as well as the microstrip lines used for the matching network are analyzed.

DTMOS Low Noise Amplifier Design in Partially Depleted SOI CMOS Technology

This paper reviews and analyzes a low-noise amplifier (LNA) for low-power applications using a cascode inductive source degeneration topology, with a dynamic threshold MOSFET (DTMOS) transistor in 130 nm CMOS SOI technology. Thanks to the introduction of dynamic threshold-voltage MOSFET (DTMOS), the measurement of the LNA shows 13 dB gain and -30 dB reflection input, while dissipating 6 mW under 1.2 V supply