N. Fel

Low power 23-GHz and 27-GHz distributed cascode amplifiers in a standard 130nm SOI CMOS process

Two fully integrated distributed amplifiers (DA) were designed using a standard 130 nm partially-depleted silicon-on-insulator CMOS process. They make use of either body-contacted (BC) or floating-body (FB) MOSFETs, and microstrip lines. The BC-DA has a 5.4 dB gain and a unity-gain bandwidth of 23 GHz whereas the FB-DA has a 6.8 dB gain and a unity-gain bandwidth of 27 GHz. The measured output power at 1 dB compression is 5 dBm at 5 GHz and the noise figure is 6.5-7.5 dB over 6-18 GHz for both DAs. Power consumption is 58 mW at 1.4 V.

Temperature effect on the performance of a traveling wave amplifier in 130 nm SOI technology

The behavior of an integrated traveling wave amplifier (TWA), fabricated in a 130 nm silicon-on-insulator (SOI) CMOS process, has been characterized over a temperature range from 25/spl deg/C to 250/spl deg/C. The TWA is a four-stage cascode design which uses floating body (FB) transistors and microstrip lines as passives. A gain of 7 dB with a 0.4-27 GHz bandwidth is measured under 1.4 V supply voltage. The effects of high temperature are observed on the gain of the TWA, as well as on the SOI transistors and the microstrip lines.

An investigation of temperature effects on CPW and MSL on SOI substrate for RF applications

Losses of microstrip line and coplanar waveguide made on HR and STD SOI wafers were analyzed with respect to temperature. MSL allows the use of STD substrate because the back ground plane shields the Si substrate. MSL can then be an interesting topology if the losses can be lowered to the same level than CPW made on HR SOI or SOS. For the CPW, the losses are of two kinds: conductor losses, due to the metal resistivity, and substrate losses, due to the coupling between the line and the substrate. These results demonstrate the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications. Due to the rapid increase in the number of metallic interconnects, the top level metals are situated further away from the SOI substrate as the technology scales, thus reducing the substrate losses for CPW and widen the metallic strip for MSL. In a near future, 12 metal levels are available and enable using 5 times wider strips for MSL and thus reduce the losses by a factor of 3 making MSL as a very promising structure for RF design for the next technological node.

Design of a Distributed Oscillator in 130 nm SOI MOS Technology

In this paper, the design and the results of a silicon-on-insulator (SOI) CMOS distributed amplifier (DA) and oscillator are presented. The four stage cascode DA (CDA) is designed with a 130 nm SOI floating body n-MOSFET in each stage requiring a chip area of 0.75 mm2. A gain of 7 dB and a unity-gain bandwidth of 26 GHz are measured at 1.4 V supply voltage with a measured power consumption of 54 mW. The CDA circuit has been extended to design a cascode distributed oscillator (CDO) showing a 3 dBm carrier at 10 GHz oscillating frequency, for 2.5 V supply voltage

Behavior of a common source traveling wave amplifier versus temperature in SOI technology

In this paper, the design and the results of a CMOS Silicon-On-Insulator (SOI) traveling wave amplifier (TWA) versus temperature are presented. The four stage TWA is designed with a single common source n-MOSFET in each stage using a 130 nm SOI CMOS technology requiring a chip area of 0.75 mm/sup 2/. A gain of 4.5 dB and a unity-gain bandwidth of 30 GHz are measured at 1.4 V supply voltage with a measured power consumption of 66 mW. The designed circuit has been characterized over a temperature range from 25 to 300/spl deg/C. The performance degradation on the gain of the TWA, the SOI transistors as well as the microstrip lines used for the matching network are analyzed.

Design of distributed amplifiers and oscillators in 130 nm SOI MOS technology

In this paper, the design and the results of two CMOS silicon-on-insulator (SOI) distributed amplifiers (DA) are presented. Partially-depleted SOI process using microstrip lines, and floating-body (FB) transistors are considered. The measured gain is around 4.5 dB with a 0.4-30 GHz bandwidth for the common source DA (CSDA) and around 7 dB with a 0.4-26 GHz bandwidth for the cascode DA (CDA). The optimized performances were found for 1.4 V supply voltage, which corresponds to a DC power consumption of 66 and 55 mW for the CSDA and the CDA, respectively. The CSDA circuit has been extended to design a distributed oscillator (DO) at 12 GHz, and CDA to a cascaded CDA with a cut-off frequency of 48 GHz and 8 dB gain.