Melanie Etherton

P2P and Rmap - new software tool for quick and easy verification of power nets

A new software tool, P2P, for electrical simulation of power nets is presented. The Rmap functionality of P2P calculates resistances from specified starting points to all points on the net, and visualizes the results in resistance color maps - which enables quick identification and debugging of layout errors. P2P also enables point-to-point resistance calculation, IR voltage drop analysis, and current density verification. Case studies are presented for overall power/ground net verification, and for specific tasks of guard ring and ESD device resistance and current density verification.

A new full-chip verification methodology to prevent CDM oxide failures

This paper describes a new full-chip CDM ESD verification method that enables the evaluation of complete integrated circuits (ICs) for CDM risk. We demonstrate that a robust analysis must comprehend millions of locations of driver-receiver (D/R) pairs on an IC, an accurate model of the grid resistance and an adequate representation of the CDM current distribution.

RC triggered active ESD clamps; How should they behave under powered conditions?

Problems with standard RC clamp circuits during powered system level ESD events are reviewed. A new clamp design is presented which employs a proportional triggering scheme that regulates the pad voltage during transient events, rather than simply switching the clamps fully on or off.

Electronic design automation (EDA) solutions for ESD-robust design and verification

The paper describes the essential requirements of the Electrostatic Discharge (ESD) EDA verification flow to be aligned within the IC design community. The proposed flow offers a systematic approach to check ESD robustness across all IC blocks during the product definition, chip architecture, main module and full IC design phases, and during the final IC verification. This flow is substantiated by case studies of key ESD checks at different IC design stages, demonstrating the necessity of replacing manual checks with EDA tool enabled verification.