Michael G. Khazhinsky

Engineering the cascoded NMOS output buffer for maximum V/sub t1/

The overall ESD performance of CMOS integrated circuits is often limited by the ESD robustness of the lateral NPN (LNPN) bipolar transistor parasitic to the NMOS output buffer. In this paper, we investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer. Based on experimental data and device simulations, we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout; and (2) how V/sub t1/ may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.

Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

In this paper we propose new circuit design options for increasing the ldquoeffectiverdquo failure voltage (Vt2) of both NMOS and PMOS output buffer transistors, thereby helping to protect these fragile devices. Using experimental data, device and circuit simulations we demonstrate how placing a series resistor and either a bias circuit for the buffer gates or secondary ESD diodes may significantly increase Vt2.

ESD protection strategies in advanced CMOS SOI ICs

This paper represents a part of the ESREF 2007 tutorial on the design of IC protection circuits built with advanced deep sub-micron CMOS silicon-on-insulator (SOI) technologies. The tutorial covers fundamental aspects of active rail clamp Electrostatic Discharge (ESD) protection approach to meet the human body model (HBM), machine model (MM), and charged device model (CDM) requirements in SOI ICs. The paper focuses on 65 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. It compares pulsed measurement results of SOI MOSFETs and diodes to bulk devices. It also introduces a response surface method (RSM) to optimize device sizes in the ESD networks.

Study of undoped channel FinFETs in active rail clamp ESD networks

In this paper we investigate state-of-the-art undoped channel FinFETs and FinDiodes with an emphasis on I/O and ESD applicability. Utilizing electrical characterization data, 3D TCAD, and a compact model, we demonstrate that FinFETs and FinDiodes exhibit a very appealing combination of high breakdown voltage and low Ioff for I/O and ESD protection circuit applications.