Shin-Jang Shen

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

Numerous low-supply-voltage (VDD) mobile chips, such as energy-harvesting-powered devices and biomedical applications, require low-VDD on-chip nonvolatile memory (NVM) for low-power active-mode access and power-off data storage. However, conventional NVMs cannot achieve low-VDD operation due to insufficient write voltage generated by charge-pumped (CP) circuits at a low VDD, and a lack of low-VDD current-mode sense amplifiers (CSA) [1-4] to overcome read issues in reduced sensing margins, degraded speeds, and insufficient voltage headroom (VHR). Resistive RAM (ReRAM) [4-6] is a promising memory with the advantages of short write time, low write-voltage, and reduced write power compared to Flash and other NVMs. Using a low-VDD CP with relaxed output voltage/current requirements for write operations, ReRAM is a good candidate for on-chip low-VDD NVM if a low-VDD CSA is provided, particularly for frequent-read-seldom-write applications. We develop a body-drain-driven CSA (BDD-CSA) with dynamic BL bias voltage (VBL) and small VHR for larger sensing margins to achieve a lower VDDmin, faster read speed, and better tolerance of read cell current (ICELL) and BL leakage current (IBL-LEAK) variations compared to conventional CSAs. A fabricated 65nm 4Mb ReRAM macro using the BDD-CSA and our CMOS-logic-compatible ReRAM cell [7] achieves 0.5V VDDmin. The BDD-CSA achieves 0.32V VDDmin.

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Decreasing read cell current (<i>I</i>_CELL) has become a major trend in nonvolatile memory (NVM). However, a reduced <i>I</i>_CELL leaves the operation of the sense amplifier (SAs) vulnerable to bitline (BL) level offset and SA input offset. Thus, small- <i>I</i>_CELL NVMs suffer from slow read speed or low read yield. In this study, we propose a new current-sampling-based SA (CSB-SA) to suppress the offset due to device mismatch, while maintaining tolerance for insufficient precharge time. These features enable CSB-SA to achieve a read speed 6.3 ×-8.1× faster than previous SAs, for sensing 100 nA <i>I</i>_CELLs on a 2 K-cell bitline. We fabricated a CMOS-logic-compatible, 90 nm, 512 Kb OTP macro, using the CSB-SA. This OTP macro achieves a random access time of 26 ns for reading sub-200 nA <i>I</i>_CELL. Measurements confirm that this 90 nm CSB-SA is also capable of sub-100 nA sensing.

A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme

Replica-cell sensing schemes are commonly used in the read circuits of flash memories to provide the appropriate reference current across various process, voltage and temperature (PVT) conditions. However, process variation on the replica array causes fluctuations in the settling time and the value of the reference current across dies or wafers, especially in split-gate flash memories. A long settling time of reference current slows down the access time, and causes ringing on outputs. Fluctuation in the reference current produces various sensing margins, and decreases the yield, due to tail bits. A circuit-level technique for embedded flash memories, called pre-stable current sensing (PSCS), is proposed to reduce the fluctuation in access time and sensing margin, without additional masks or process steps. Experiments on fabricated flash macros (4 Mb, 2 Mb, 1 Mb, and 512 Kb) using a 0.25 mum embedded flash process demonstrate that PSCS achieves uniform access time across hundreds of samples. Additionally, PSCS works with a wide range of supply voltages (1.1-3 V).

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro

ReRAM is a promising candidate for on-chip low-VDD NVM due to its superior write behavior, particularly for frequent-read-seldom-write applications. Nonetheless, this approach requires a robust and fast low-VDD read scheme. Current-mode sense amplifiers (CSA) are commonly used in NVM; however, they suffer low-yield and degraded speed at a low VDD, due to an insufficient on-off current difference ( I ON-OFF) and the need for large voltage head room (VHR). This study developed a body-drain-driven (BDD) read scheme to suppress VHR and provide resistance-aware dynamic bitline bias voltage for increasing I ON-OFF. The proposed scheme achieved 2.1 × faster read speed, > 1.7× higher yield, and > 2× longer BL length at 0.5 V VDD than conventional CSAs. A fabricated 65 nm 4 Mb ReRAM macro using the proposed read scheme and our logic-compatible ReRAM cell achieved a 45 ns random read access time at VDD=0.5 V. The proposed sensing scheme also achieved a 0.32 V VDDmin.

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Current-mode sense amplifiers (CSA) are commonly used in eNVM, because of their fast read speed at large bitline (BL) loads and small cell read currents. However, conventional CSAs are unable to achieve fast random read access time (TAC), due to significant summed input offsets (IOS-SUM) at read-path. This work proposes a calibration-based asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS-SUM and enable high-speed sensing without the need for run-time offset-cancellation operations. This work then fabricated two 90 nm AVB-CSA 1 Mb Flash testchips (with and without BL-length test-modes). The AVB-CSA eFlash macros with 512 rows achieved TAC of 3.9 ns at nominal VDD (1.2 V). The BL-length test-mode experiments confirmed a 1.53× improvement in TAC using AVB-CSA with a BL-length of 2048-rows operating at VDD=0.8 V.

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

Decreasing read cell current (ICELL) has become a key trend in nonvolatile memory (NVM). This is not only due to device size and VDD scaling while keeping the same threshold voltage (VTH), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1–2] to achieve smaller area-per-bit; 2) lower-VDD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller ICELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (CBL) mismatches and 2) VTH variation. As device size and BL-pitch is continually scaled down, the above factors have become major showstopper for SAs. To tolerate these offsets, small-ICELLNVMs suffer from slow read speed or high read fail probability. Thus, a more largely offset tolerant SA is a prerequisite to achieve faster read speeds. In this study, we propose a new offset tolerant current-sampling-based SA (CSB-SA) to achieve 7× faster read speed than previous SAs for sensing small ICELL. A fabricated 90nm 512Kb OTP macro, using the CSB-SA and our CMOS-logic-compatible OTP cell [4], achieves 26ns macro random access time for reading sub-200nA ICELL. Measurements also confirmed that this 90nm CSB-SA could achieve sub-100nA sensing.

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

3D vertical-gate (3DVG) NAND flash is a promising candidate for next-generation high-density nonvolatile memory. Cross-layer process variation renders 3DVG NAND susceptible to decreased speeds, yield, and reliability. This can be attributed to (a) cross-layer mismatch in bitline capacitance (CBL), (b) the need for long program cycles, and (c) sensing-margin (SM) loss induced by the effects of background-pattern-dependency (BPD). This study proposes three circuit-level techniques to overcome these issues by employing the following: (1) distributed NAND-string scramble (DNSS), (2) layer-aware program-verify-and-read (LA-PV-R), and (3) a layer-aware-bitline-precharge (LA-BP) scheme. For an 8-layer 3DVG with 200 mV cross-layer mismatch in cell threshold voltage ( V THC), DNSS reduces the cross-layer C BL-mismatch by 41%, LA-PV-R using various program-threshold-voltages ( V THP) for each layer enables a 25% reduction in the number of program cycles, and LA-BP succeeds in reducing BPD-induced SM loss by 56%. A 2-layer 3DVG NAND testchip and 8-layer testkey were fabricated to evaluate the proposed methods. The LA-PV-R and LA-BP have achieved a 0.75 V difference in V THP between layer-0 and layer-1 with a 0.4V difference in BL clamping bias voltages and the LA-BP scheme has achieved a 44% reduction in BPD-induced SM loss. The three proposed schemes incur an area penalty of less than 0.1% in a Gb-scale 3DVG NAND device.

Supply-variation-resilient nonvolatile 3D IC and 3D memory using low peak-current on-chip charge-pump circuits

In heterogeneous nonvolatile 3D-ICs, nonvolatile memory modules are used to enable reliable computing and smart power on-off management as a means of suppressing system standby current. This paper discusses the challenges caused by supply noise variations in 3D-IC and 3D-memory modules, including 3D-RAM, 3D monolithic ICs, vertical-device-stacking nonvolatile-SRAM, and 3D vertical-gate NAND flash. Cross-layer supply noise in 3D-IC and 3D-memory is reduced by implementing low peak-current on-chip charge-pump (CP) circuits using a split asymmetrically shifted clocking (SAS) scheme. A fabricated 90nm testchip with SAS and conventional CPs confirms that the proposed scheme is able to reduce power noise by 60+% and improves power efficiency by 7% with an area penalty of less than 3%, compared to a conventional CP operating at the same frequency.

A sub-0.5V charge pump circuit for resistive RAM (ReRAM) enabled low supply voltage nonvolatile logics and nonvoaltile processors

Many processors that use energy harvesting devices for low-power computing operations and zero-standby-current power-off storage require embedded nonvolatile memory (eNVM) devices and nonvolatile logics (nvLogics) with low-voltage capability. However, conventional eNVMs and nvLogics are unable to perform low-voltage write operations due to a failure on the part of on-chip charge-pump circuits to provide the high write voltage and write current required by NVM devices under low supply voltage (VDD). This study developed hybrid-boost-voltage (HBV) and hybrid-device (HD) schemes for a single-supply charge pump to enable low-VDD operations with sufficient voltage and current for the write operation of ReRAM-based eNVM and nvLogics. A HBV-HD CP fabricated in a 65nm testchip achieved VDDmin ofless than 0.5V.

An embedded flash macro with sub-4ns random-read-access using asymmetric-voltage-biased current-mode sensing scheme

High-performance mobile chips and MCUs require large-capacity and fast-read embedded nonvolatile/Flash memory (eNVM/eFlash) for code and data storage. Current-mode sense amplifiers (CSA) are commonly used in eNVM due to their fast sensing against large bitline (BL) load and small cell read currents. However, conventional CSAs cannot achieve fast random read access time (TAC) due to significant summed read-path input offsets (IOS-SUM). This work proposes an asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS-SUM and enable high-speed sensing without run-time offset-cancellation operations. A 90nm AVB-CSA 1Mb Flash macro with BL-length test-modes was fabricated. The 512-rows AVB-CSA eFlash macro achieves 3.9ns TAC. The test-mode experiments confirmed that AVB-CSA improves 1.48x in TAC for 2048-rows BL-length. For the first time, a Mb eFlash with long BL achieves sub-4ns TAC.