Yi-Bo Liao

Temperature-based phase change memory model for pulsing scheme assessment

A physical yet analytical phase change memory (PCM) model simultaneously accounting for thermal and electrical conductivities is presented. Due to the physics based nature of the model, the essential temperature from heating and cooling of PCM during operation is instantaneously updated. More importantly, the model can be applied to non-conventional circuit design technique. We show that for the first time the input current pulsing scheme for PCM programming can be significantly simplified via the unique intrinsic thermal memory effect. The model is implemented in HSPICE using Verilog-A, which is flexible and portable for different circuit simulators. As PCM technology is emerging, the predictive compact model can expedite the novel technology development.

An Analytical Compact PCM Model Accounting for Partial Crystallization

This paper presents a simple yet predictive compact model for phase change memory (PCM). We successfully implement the model in a circuit simulator using Verilog-A. Due to the physical nature of the model, it can be used to predict the temperature and crystalline fraction in the cell, simply via SPICE simulation. This paper also demonstrates the use of the model in static resistance calculation, i.e. the set and reset statuses in R-I characteristics. More importantly, the crystal status transitions such as partial crystalline and amorphous statuses, resulting in uncertain resistance, are accounted for. The model can facilitate the PCM technology development not only in the device level, but also in the circuit level.

Design optimization in write speed of multi-level cell application for phase change memory

Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.

Phase change memory modeling using Verilog-A

In this paper, we successfully develop a compact phase change memory (PCM) model using Verilog-A. As PCM has shown its potential for next generation memory device, a predictive, yet simple-to-use circuit model is crucial to the development. Since the Verilog-A modeling is flexible and portable for many circuit simulators, the proposed modeling technique can be widely used, as compared with conventional modeling schemes.

Stack Gate Technique for Feasible Bulk FinFETs

Yi-Bo Liao, Meng-Hsueh Chiang, Wei-Chou Hsu, Yu-Sheng Lai, and Hsun Li Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, 701 Tainan, Taiwan Department of Electric Engineering, National Ilan University, 260 I-Lan, Taiwan National Nano Device Laboratories, 300 Hsinchu, Taiwan Phone: +886-9-357400 ext. 653, Fax: +886-9-9369507, E-mail: mhchiang@niu.edu.tw

Assessment of novel phase change memory programming techniques

In this paper, we present novel phase change memory programming techniques achieving low power operation without compromising performance by using proper pulsing schemes. By applying continuous current pulses at a fixed frequency or with the same pulse magnitude, binary data are successfully written into memory cells. The proposed programming techniques can be implemented with more flexible or simplified circuitry since a single current level is shown to be sufficient for write operations of both set and reset states.

Low power design of phase-change memory based on a comprehensive model

In this study, the authors propose non-conventional phase-change memory programming schemes using a comprehensive model, which integrates the underlying electrical and thermal theories. Various pulsing schemes aiming to reduce operation power without compromising performance are assessed based on a calibrated model. Our results suggest that optimisation of power consumption can be done simply by design of pulsing techniques.

Optimal design and performance assessment of extremely-scaled si nanowire FET on insulator

Optimal design for nanowire FETs beyond 22 nm technology node is presented using numerical 3D simulation and physical analysis. Our results suggest that design optimization associated with the wire diameter could achieve performance benefits in the nanowire FET technologies. Small wire diameter is not necessary for performance, though it favors device scaling.

Scaling study of nanowire and multi-gate MOSFETs

In this paper, comprehensive comparisons of nanowire and multi-gate nMOSFETs in scaling capability using three-dimensional numerical simulations are presented. Their short channel effects and device performances are also investigated. The nanowire device requires less device dimension constraint on body diameter due to perfect surrounding gate-to-gate capacitive coupling and hence it is promising at sub-45 nm node.